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* [globalisel] Tablegen-erate current Register Bank InformationDaniel Sanders2017-01-164-1/+317
| | | | | | | | | | | | | | Summary: Adds a RegisterBank tablegen class that can be used to declare the register banks and an associated tablegen pass to generate the necessary code. Reviewers: t.p.northover, ab, rovka, qcolombet Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka Differential Revision: https://reviews.llvm.org/D27338 llvm-svn: 292132
* [X86] Merge the disassemblers handling of the different TYPE_RELs by getting ↵Craig Topper2017-01-161-6/+6
| | | | | | the size information from the ENCODING field. NFCI llvm-svn: 292096
* [X86] Reduce the number of operand 'types' the disassembler needs to deal ↵Craig Topper2017-01-161-87/+86
| | | | | | | | | with. NFCI We were frequently checking for a list of types and the different types conveyed no real information. So lump them together explicitly. llvm-svn: 292095
* [AVX-512] Begin giving the disassembler a way to recognize that VSIB is a ↵Craig Topper2017-01-161-15/+17
| | | | | | | | different encoding than regular addressing modes. This part first teaches it not to check error if EVEX.V2 is used by a VSIB instruction. llvm-svn: 292093
* [AVX-512] Correct memory operand size for VPGATHERQPS and VPGATHERQDCraig Topper2017-01-161-0/+2
| | | | | | | | | with ZMM index. Similar for SCATTER and the prefetch gather and scatter instructions. Fixes PR31618. llvm-svn: 292088
* Mark comparator call operator as constEric Fiselier2016-12-271-1/+1
| | | | llvm-svn: 290636
* [GlobalISel] Add basic Selector-emitter tblgen backend.Ahmed Bougacha2016-12-215-1/+399
| | | | | | | | | | | | | | | | | This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
* [TableGen] Use 'unsigned' instead of 'bool' in a place where the code ↵Craig Topper2016-12-191-1/+1
| | | | | | conditionally assigns numeric values. They happen to be 0 and 1 so this is NFC. llvm-svn: 290088
* Implement LaneBitmask::any(), use it to replace !none(), NFCIKrzysztof Parzyszek2016-12-162-5/+5
| | | | llvm-svn: 289974
* Fix ubsan failures in lane mask shiftsKrzysztof Parzyszek2016-12-151-4/+8
| | | | llvm-svn: 289826
* Extract LaneBitmask into a separate typeKrzysztof Parzyszek2016-12-153-66/+73
| | | | | | | | | | | | Specifically avoid implicit conversions from/to integral types to avoid potential errors when changing the underlying type. For example, a typical initialization of a "full" mask was "LaneMask = ~0u", which would result in a value of 0x00000000FFFFFFFF if the type was extended to uint64_t. Differential Revision: https://reviews.llvm.org/D27454 llvm-svn: 289820
* [AMDGPU, PowerPC, TableGen] Fix some Clang-tidy modernize and Include What ↵Eugene Zelenko2016-12-121-10/+14
| | | | | | You Use warnings; other minor fixes (NFC). llvm-svn: 289475
* [AMDGPU, PowerPC, TableGen] Fix some Clang-tidy modernize and Include What ↵Eugene Zelenko2016-12-091-13/+14
| | | | | | You Use warnings; other minor fixes (NFC). llvm-svn: 289282
* Summary: Currently there is no way to disable deprecated warning from asm ↵Weiming Zhao2016-12-051-1/+3
| | | | | | | | | | | | | | | | | | | | like this clang -target arm deprecated-asm.s -c deprecated-asm.s:30:9: warning: use of SP or PC in the list is deprecated stmia r4!, {r12-r14} We have to have an option what can disable it. Patched by Yin Ma! Reviewers: joey, echristo, weimingz Subscribers: llvm-commits, aemerson Differential Revision: https://reviews.llvm.org/D27219 llvm-svn: 288734
* TableGen/AsmMatcherEmitter: Bring sorting check back under EXPENSIVE_CHECKSMatthias Braun2016-12-051-3/+13
| | | | | | | | | | | Bring the sorting check back that I removed in r288655 but put it under EXPENSIVE_CHECKS this time. Also document that this the check isn't purely about having a sorted list but also about operator < having the correct transitive behavior. Apply the same to the other check in the file. llvm-svn: 288693
* TableGen/AsmMatcherEmitter: Trust that stable_sort worksMatthias Braun2016-12-051-10/+0
| | | | | | | | | A debug build of AsmMatcherEmitter would use a quadratic algorithm to check whether std::stable_sort() actually sorted. Let's hope the authors of our C++ standard library did that testing for us. Removing the check gives a 3x speedup in the X86 case. llvm-svn: 288655
* TableGen: Use StringInit instead of std::string for DagInit arg namesMatthias Braun2016-12-054-30/+34
| | | | llvm-svn: 288644
* TableGen: Use StringInit instead of std::string for DagInit nameMatthias Braun2016-12-051-4/+4
| | | | llvm-svn: 288643
* TableGen: Use StringRef instead of const std::string& in return vals.Matthias Braun2016-12-0418-37/+40
| | | | | | | This will allow to switch to a different string storage in an upcoming commit. llvm-svn: 288612
* [tablegen] Delete duplicates from a vector without skipping elementsVedant Kumar2016-12-011-0/+1
| | | | | | | | | | | | | | Tablegen's -gen-instr-info pass has a bug in its emitEnums() routine. The function intends for values in a vector to be deduplicated, but it accidentally skips over elements after performing a deletion. I think there are smarter ways of doing this deduplication, but we can do that in a follow-up commit if there's interest. See the thread: [PATCH] TableGen InstrMapping Bug fix. Patch by Tyler Kenney! llvm-svn: 288408
* Fix some Clang-tidy and Include What You Use warnings; other minor fixes (NFC).Eugene Zelenko2016-11-307-132/+219
| | | | | | This preparation to remove SetVector.h dependency on SmallSet.h. llvm-svn: 288256
* Apply clang-tidy's 'performance-faster-string-find' check to LLVM.Benjamin Kramer2016-11-301-1/+1
| | | | | | No functionality change intended. llvm-svn: 288235
* TableGen: Allow signed immediates for instruction aliasesJacob Baungard Hansen2016-11-241-1/+1
| | | | | | | | | | | | Patch by Daniel Cederman. Reviewers: stoklund, arsenm Subscribers: arsenm, llvm-commits Differential Revision: https://reviews.llvm.org/D27046 llvm-svn: 287856
* Add IntrInaccessibleMemOnly property for intrinsicsAndrew Kaylor2016-11-223-7/+60
| | | | | | Differential Revision: https://reviews.llvm.org/D26485 llvm-svn: 287680
* [TableGen][ISel] When factoring ScopeMatcher, if the child of the ↵Craig Topper2016-11-221-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ScopeMatcher we're working on is also a ScopeMatcher, merge all its children into the one we're working on. There were several cases in X86 where we were unable to fully factor a ScopeMatcher but created nested ScopeMatchers for some portions of it. Then we created a SwitchType that split it up and further factored it so that we ended up with something like this: SwitchType Scope Scope Sequence of matchers Some other sequence of matchers EndScope Another sequence of matchers EndScope ...Next type This change turns it into this: SwitchType Scope Sequence of matchers Some other sequence of matchers Another sequence of matchers EndScope ...Next type Several other in-tree targets had similar nested scopes like this. Overall this doesn't save many bytes, but makes the isel output a little more regular. llvm-svn: 287624
* [Sparc] Use target name instead of namespace as prefix for MCRegisterClasses ↵Jacob Baungard Hansen2016-11-211-1/+1
| | | | | | | | | | | | | | | | | | | array Summary: For Sparc the namespace (SP) is different from the target name (Sparc), which causes the name of the array in this declaration to differ from the name used in the definition. Patch by Daniel Cederman. Reviewers: jyknight Subscribers: llvm-commits, jyknight Differential Revision: https://reviews.llvm.org/D23650 llvm-svn: 287528
* [TableGen][ISel] Do a better job of factoring ScopeMatchers created during ↵Craig Topper2016-11-211-3/+11
| | | | | | | | | | creation of SwitchTypeMatcher. Previously we were factoring when the ScopeMatcher was initially created, but it might get more Matchers added to it later. Delay factoring until we have fully created/populated the ScopeMatchers. This reduces X86 isel tables by 154 bytes. llvm-svn: 287520
* Try again to fix unused variable warning on lld-x86_64-darwin13 after r287439.Daniel Sanders2016-11-191-1/+6
| | | | | | | The previous attempt didn't work. I assume LLVM_ATTRIBUTE_UNUSED isn't available on that machine. llvm-svn: 287442
* Check that emitted instructions meet their predicates on all targets except ↵Daniel Sanders2016-11-196-30/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | ARM, Mips, and X86. Summary: * ARM is omitted from this patch because this check appears to expose bugs in this target. * Mips is omitted from this patch because this check either detects bugs or deliberate emission of instructions that don't satisfy their predicates. One deliberate use is the SYNC instruction where the version with an operand is correctly defined as requiring MIPS32 while the version without an operand is defined as an alias of 'SYNC 0' and requires MIPS2. * X86 is omitted from this patch because it doesn't use the tablegen-erated MCCodeEmitter infrastructure. Patches for ARM and Mips will follow. Depends on D25617 Reviewers: tstellarAMD, jmolloy Subscribers: wdng, jmolloy, aemerson, rengolin, arsenm, jyknight, nemanjai, nhaehnle, tstellarAMD, llvm-commits Differential Revision: https://reviews.llvm.org/D25618 llvm-svn: 287439
* [tablegen] Merge duplicate definitions of getMinimalTypeForRange. NFC.Daniel Sanders2016-11-196-37/+72
| | | | | | | | | | | | Summary: Depends on D25614 Reviewers: qcolombet Subscribers: qcolombet, beanz, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D25617 llvm-svn: 287438
* Fix -Wunused introduced in r286945 for release builds.Daniel Sanders2016-11-151-0/+2
| | | | llvm-svn: 286946
* [tablegen] Extract portions of AsmMatcherEmitter for re-use by another ↵Daniel Sanders2016-11-154-89/+158
| | | | | | | | | | | | | | | | | | | generator. NFC. Summary: This change is preparation for a change that will allow targets to verify that the instructions they emit meet the predicates they specify. This is useful to ensure that C++ legalization/lowering/instruction-selection doesn't incorrectly select code for a different subtarget than intended. Such cases are not caught by the integrated assembler when emitting instructions directly to an object file. Reviewers: qcolombet Subscribers: qcolombet, beanz, mgorny, llvm-commits, modocache Differential Revision: https://reviews.llvm.org/D25614 llvm-svn: 286945
* Re-apply r286384, "X86: Introduce the "relocImm" ComplexPattern, which ↵Peter Collingbourne2016-11-093-7/+13
| | | | | | | | | represents a relocatable immediate.", with a fix for 32-bit x86. Teach X86InstrInfo::analyzeCompare() not to crash on CMP and SUB instructions that take a global address operand. llvm-svn: 286420
* Revert r286384, "X86: Introduce the "relocImm" ComplexPattern, which ↵Peter Collingbourne2016-11-093-13/+7
| | | | | | | | | represents a relocatable immediate." Suspected to be the cause of a sanitizer-windows bot failure: Assertion failed: isImm() && "Wrong MachineOperand accessor", file C:\b\slave\sanitizer-windows\llvm\include\llvm/CodeGen/MachineOperand.h, line 420 llvm-svn: 286385
* X86: Introduce the "relocImm" ComplexPattern, which represents a relocatable ↵Peter Collingbourne2016-11-093-7/+13
| | | | | | | | | | | | | | | immediate. A relocatable immediate is either an immediate operand or an operand that can be relocated by the linker to an immediate, such as a regular symbol in non-PIC code. Start using relocImm for 32-bit and 64-bit MOV instructions, and for operands of type "imm32_su". Remove a number of now-redundant patterns. Differential Revision: https://reviews.llvm.org/D25812 llvm-svn: 286384
* Expandload and Compressstore intrinsicsElena Demikhovsky2016-11-032-6/+8
| | | | | | | | 2 new intrinsics covering AVX-512 compress/expand functionality. This implementation includes syntax, DAG builder, operation lowering and tests. Does not include: handling of illegal data types, codegen prepare pass and the cost model. llvm-svn: 285876
* [TableGen] Move OperandMatchResultTy enum to MCTargetAsmParser.hAlex Bradbury2016-11-011-9/+2
| | | | | | | | | | | | | | | As it stands, the OperandMatchResultTy is only included in the generated header if there is custom operand parsing. However, almost all backends make use of MatchOperand_Success and friends from OperandMatchResultTy for e.g. parseRegister. This is a pain when starting an AsmParser for a new backend that doesn't yet have custom operand parsing. Move the enum to MCTargetAsmParser.h. This patch is a prerequisite for D23563 Differential Revision: https://reviews.llvm.org/D23496 llvm-svn: 285705
* Fix per-processor model scheduler definition completeness checkUlrich Weigand2016-10-311-1/+2
| | | | | | | | | | | | | | | The CodeGenSchedModels::checkCompleteness routine in TableGen/ CodeGenSchedule.cpp is supposed to verify for each processor model that is marked as "complete" that it actually defines a scheduling class for each instruction. However, this did not work correctly due to an incorrect check whether a scheduling class has an itinerary. Reviewer: atrick Differential revision: https://reviews.llvm.org/D26156 llvm-svn: 285622
* Revert 285087.Nico Weber2016-10-251-0/+8
| | | | | | | | | | | | | The sanitizer-windows bot turned red with: FAILED: utils/TableGen/CMakeFiles/obj.llvm-tblgen.dir/IntrinsicEmitter.cpp.obj C:\PROGRA~2\MICROS~1.0\VC\bin\AMD64_~2\cl.exe ... -c C:\...\llvm\utils\TableGen\IntrinsicEmitter.cpp c:\...\llvm\utils\tablegen\intrinsicemitter.cpp(254) : fatal error C1001: An internal error has occurred in the compiler. http://lab.llvm.org:8011/builders/sanitizer-windows/builds/114/steps/build%20clang%20lld/logs/stdio llvm-svn: 285089
* Try removing an MSVC2010 workaround.Nico Weber2016-10-251-8/+0
| | | | | | | Things seem to build fine locally without this, so let's see what the bots think. llvm-svn: 285087
* Switch SmallSetVector to use DenseSet when it overflows its inline space.Justin Lebar2016-10-212-20/+23
| | | | | | | | | | | | | | | | | | | | Summary: SetVector already used DenseSet, but SmallSetVector used std::set. This leads to surprising performance differences. Moreover, it means that the set of key types accepted by SetVector and SmallSetVector are quite different! In order to make this change, we had to convert some callsites that used SmallSetVector<std::string, N> to use SmallSetVector<CachedHashString, N> instead. Reviewers: timshen Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25648 llvm-svn: 284887
* Improve tablegen gen-subtarget diagnostics for missing machine models.Andrew Trick2016-10-181-5/+8
| | | | | | | | | | | | -debug-only=subtarget-emitter prints a lot of machine model diagnostics. This prunes the output so that the "No machine model for XXX on processor YYY" only appears when there is definitely no machine model for that opcode. Previously it was printing that error even if the opcode was covered by a more general scheduling class. <rdar://problem/15919845> [TableGen][CodeGenSchedule] Debug output does not help spotting the missing scheduling classes llvm-svn: 284452
* Revert r283690, "MC: Remove unused entities."Peter Collingbourne2016-10-101-1/+1
| | | | llvm-svn: 283814
* Use StringRef in TableGen generated Intrinsics.gen file (NFC)Mehdi Amini2016-10-101-7/+5
| | | | llvm-svn: 283792
* MC: Remove unused entities.Peter Collingbourne2016-10-091-1/+1
| | | | llvm-svn: 283691
* Turn cl::values() (for enum) from a vararg function to using C++ variadic ↵Mehdi Amini2016-10-081-2/+1
| | | | | | | | | | | | | | | template The core of the change is supposed to be NFC, however it also fixes what I believe was an undefined behavior when calling: va_start(ValueArgs, Desc); with Desc being a StringRef. Differential Revision: https://reviews.llvm.org/D25342 llvm-svn: 283671
* FastISel: Remove unused/un-overridden entry points. NFCI.Peter Collingbourne2016-10-051-2/+1
| | | | llvm-svn: 283366
* Use StringRef in TableGen (NFC)Mehdi Amini2016-10-042-3/+3
| | | | llvm-svn: 283273
* Use StringRef in TableGen emitted API for attribute (NFC)Mehdi Amini2016-10-041-1/+1
| | | | llvm-svn: 283268
* Use StringRef for MemoryBuffer identifier API (NFC)Mehdi Amini2016-10-011-1/+1
| | | | llvm-svn: 283043
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