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| author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2016-10-31 18:59:52 +0000 |
|---|---|---|
| committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2016-10-31 18:59:52 +0000 |
| commit | 75cda2f2b50f7872e129f700663251711a3a2923 (patch) | |
| tree | 353da5e629f2bdda9b920dd8a6ada51912361b74 /llvm/utils/TableGen | |
| parent | 63b4a37ef56e21490dfb0bc4148f992f713f87cb (diff) | |
| download | bcm5719-llvm-75cda2f2b50f7872e129f700663251711a3a2923.tar.gz bcm5719-llvm-75cda2f2b50f7872e129f700663251711a3a2923.zip | |
Fix per-processor model scheduler definition completeness check
The CodeGenSchedModels::checkCompleteness routine in TableGen/
CodeGenSchedule.cpp is supposed to verify for each processor
model that is marked as "complete" that it actually defines a
scheduling class for each instruction.
However, this did not work correctly due to an incorrect
check whether a scheduling class has an itinerary.
Reviewer: atrick
Differential revision: https://reviews.llvm.org/D26156
llvm-svn: 285622
Diffstat (limited to 'llvm/utils/TableGen')
| -rw-r--r-- | llvm/utils/TableGen/CodeGenSchedule.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp index eb7899ea92c..4cc600d059b 100644 --- a/llvm/utils/TableGen/CodeGenSchedule.cpp +++ b/llvm/utils/TableGen/CodeGenSchedule.cpp @@ -1567,7 +1567,8 @@ void CodeGenSchedModels::checkCompleteness() { const CodeGenSchedClass &SC = getSchedClass(SCIdx); if (!SC.Writes.empty()) continue; - if (SC.ItinClassDef != nullptr) + if (SC.ItinClassDef != nullptr && + SC.ItinClassDef->getName() != "NoItinerary") continue; const RecVec &InstRWs = SC.InstRWs; |
