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* TableGen: Add MinAlignment predicateMatt Arsenault2019-07-313-2/+65
| | | | | | | | | | AMDGPU uses some custom code predicates for testing alignments. I'm still having trouble comprehending the behavior of predicate bits in the PatFrag hierarchy. Any attempt to abstract these properties unexpectdly fails to apply them. llvm-svn: 367373
* AMDGPU: Avoid emitting "true" predicatesMatt Arsenault2019-07-304-4/+15
| | | | | | | | | | Empty condition strings are considerde always true. This removes a lot of clutter from the generated matcher tables. This shrinks the source size of AMDGPUGenDAGISel.inc from 7.3M to 6.1M. llvm-svn: 367326
* TableGen: Support physical register inputs > 255Matt Arsenault2019-07-223-11/+27
| | | | | | | This was truncating register value that didn't fit in unsigned char. Switch AMDGPU sendmsg intrinsics to using a tablegen pattern. llvm-svn: 366695
* [AMDGPU] Allow register tuples to set asm namesStanislav Mekhanoshin2019-07-191-3/+12
| | | | | | | | | | | | This change reverts most of the previous register name generation. The real problem is that RegisterTuple does not generate asm names. Added optional operand to RegisterTuple. This way we can simplify register name access and dramatically reduce the size of static tables for the backend. Differential Revision: https://reviews.llvm.org/D64967 llvm-svn: 366598
* [Attributor] Deduce "willreturn" function attributeHideto Ueno2019-07-173-2/+18
| | | | | | | | | | | | | | | | | Summary: Deduce the "willreturn" attribute for functions. For now, intrinsics are not willreturn. More annotation will be done in another patch. Reviewers: jdoerfert Subscribers: jvesely, nhaehnle, nicholas, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63046 llvm-svn: 366335
* [TableGen] Do not set ReadNone attribute on intrinsics with side effectsMomchil Velikov2019-07-172-2/+4
| | | | | | | | | | | If an intrinsic is defined without outputs, but having side effects, it still can be removed completely from the program. This patch makes TableGen not set Attribute::ReadNone for intrinsics which are declared with IntrHasSideEffects. Differential Revision: https://reviews.llvm.org/D64414 llvm-svn: 366312
* [TableGen] Generate offsets into a flat array for getOperandTypeJustin Bogner2019-07-161-25/+38
| | | | | | | | | | Rather than an array of std::initializer_list, generate a table of offsets and a flat array of the operands for getOperandType. This is a bit more efficient on platforms that don't manage to get the array of inintializer_lists initialized at link time (I'm looking at you macOS). It's also quite quite a bit faster to compile. llvm-svn: 366278
* [TableGen] Add "getOperandType" to get operand types from opcode/opidxJustin Bogner2019-07-161-4/+57
| | | | | | | | | | | | | The InstrInfoEmitter outputs an enum called "OperandType" which gives numerical IDs to each operand type. This patch makes use of this enum to define a function called "getOperandType", which allows looking up the type of an operand given its opcode and operand index. Patch by Nicolas Guillemot. Thanks! Differential Revision: https://reviews.llvm.org/D63320 llvm-svn: 366274
* [WebAssembly] Rename except_ref type to exnrefHeejin Ahn2019-07-151-1/+1
| | | | | | | | | | | | | | | | | | | Summary: We agreed to rename `except_ref` to `exnref` for consistency with other reference types in https://github.com/WebAssembly/exception-handling/issues/79. This also renames WebAssemblyInstrExceptRef.td to WebAssemblyInstrRef.td in order to use the file for other reference types in future. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64703 llvm-svn: 366145
* TableGen/GlobalISel: Fix handling of truncstore patternsMatt Arsenault2019-07-151-1/+8
| | | | | | | | | | | | This was failing to import the AMDGPU truncstore patterns. The truncating stores from 32-bit to 8/16 were then somehow being incorrectly selected to a 4-byte store. A separate check is emitted for the LLT size in comparison to the specific memory VT, which looks strange to me but makes sense based on the hierarchy of PatFrags used for the default truncstore PatFrags. llvm-svn: 366129
* TableGen: Add address space to matchersMatt Arsenault2019-07-153-4/+113
| | | | | | | | | | | | | | | | | Currently AMDGPU uses a CodePatPred to check address spaces from the MachineMemOperand. Introduce a new first class property so that the existing patterns can be easily modified to uses the new generated predicate, which will also be handled for GlobalISel. I would prefer these to match against the pointer type of the instruction, but that would be difficult to get working with SelectionDAG compatbility. This is much easier for now and will avoid a painful tablegen rewrite for all the loads and stores. I'm also not sure if there's a better way to encode multiple address spaces in the table, rather than putting the number to expect. llvm-svn: 366128
* [CodeGen] Add larger vector types for i32 and f32David Majnemer2019-07-071-0/+12
| | | | | | | | | | Some out of tree backend require larger vector type. Since maintaining the changes out of tree is difficult due to the many manual changes needed when adding a new type we are adding it even if no backend currently use it. Differential Revision: https://reviews.llvm.org/D64141 Patch by Thomas Raoux! llvm-svn: 365274
* [TableGen] Allow DAG isel patterns to override default operands.Simon Tatham2019-07-043-10/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a Tablegen instruction description uses `OperandWithDefaultOps`, isel patterns for that instruction don't have to fill in the default value for the operand in question. But the flip side is that they actually //can't// override the defaults even if they want to. This will be very inconvenient for the Arm backend, when we start wanting to write isel patterns that generate the many MVE predicated vector instructions, in the form with predication actually enabled. So this small Tablegen fix makes it possible to write an isel pattern either with or without values for a defaulted operand, and have the default values filled in only if they are not overridden. If all the defaulted operands come at the end of the instruction's operand list, there's a natural way to match them up to the arguments supplied in the pattern: consume pattern arguments until you run out, then fill in any missing instruction operands with their default values. But if defaulted and non-defaulted operands are interleaved, it's less clear what to do. This does happen in existing targets (the first example I came across was KILLGT, in the AMDGPU/R600 backend), and of course they expect the previous behaviour (that the default for those operands is used and a pattern argument is not consumed), so for backwards compatibility I've stuck with that. Reviewers: nhaehnle, hfinkel, dmgreen Subscribers: mehdi_amini, javed.absar, tpr, kristof.beyls, steven_wu, dexonsmith, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63814 llvm-svn: 365114
* Teach TableGen Intrin Emitter to handle LLVMPointerType<llvm_any_ty>Erich Keane2019-06-261-0/+3
| | | | | | | | | | r363233 rewrote a bunch of the Intrin Emitter code, however the new function to update the arg codes did not properly consider a pointer to an any. This patch adds that logic. Differential Revision: https://reviews.llvm.org/D63507 llvm-svn: 364364
* Re-commit r363744: [tblgen][disasm] Allow multiple encodings to disassemble ↵Daniel Sanders2019-06-181-45/+95
| | | | | | | | | | | | | | to the same instruction It seems macOS lets you have ArrayRef<const X> even though this is apparently forbidden by the language standard (Thanks MSVC++ for the clear error message). Removed the problematic const's to fix this. (It also seems I'm not receiving buildbot emails anymore and I'm trying to find out why. In the mean time I'll be polling lab.llvm.org to hopefully see if/when failures occur) llvm-svn: 363753
* Revert [tblgen][disasm] Allow multiple encodings to disassemble to the same ↵Jordan Rupprecht2019-06-181-98/+48
| | | | | | | | | | instruction This reverts r363744 (git commit 9b2252123d1e79d2b3594097a9d9cc60072b83d9) This breaks many buildbots, e.g. http://lab.llvm.org:8011/builders/clang-atom-d525-fedora-rel/builds/203/steps/build%20stage%201/logs/stdio llvm-svn: 363747
* [tblgen][disasm] Allow multiple encodings to disassemble to the same instructionDaniel Sanders2019-06-181-48/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add an AdditionalEncoding class which can be used to define additional encodings for a given instruction. This causes the disassembler to add an additional encoding to its matching tables that map to the specified instruction. Usage: def ADD1 : Instruction { bits<8> Reg; bits<32> Inst; let Size = 4; let Inst{0-7} = Reg; let Inst{8-14} = 0; let Inst{15} = 1; // Continuation bit let Inst{16-31} = 0; ... } def : AdditionalEncoding<ADD1> { bits<8> Reg; bits<16> Inst; // You can also have bits<32> and it will still be a 16-bit encoding let Size = 2; let Inst{0-3} = 0; let Inst{4-7} = Reg; let Inst{8-15} = 0; ... } with those definitions, llvm-mc will successfully disassemble both of these: 0x01 0x00 0x10 0x80 0x00 0x00 to: ADD1 r1 Depends on D52366 Reviewers: bogner, charukcs Reviewed By: bogner Subscribers: nlguillemot, nhaehnle, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D52369 llvm-svn: 363744
* [X86Disassembler] Unify the EVEX and VEX code in emitContextTable. Merge the ↵Craig Topper2019-06-131-51/+23
| | | | | | | | | | ATTR_VEXL/ATTR_EVEXL bits. NFCI Merging the two bits shrinks the context table from 16384 bytes to 8192 bytes. Remove the ATTRIBUTE_BITS macro and just create an enum directly. Then fix the ATTR_max define to be 8192 to reflect the table size so we stop hardcoding it separately. llvm-svn: 363330
* Improve reduction intrinsics by overloading result value.Sander de Smalen2019-06-131-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch uses the mechanism from D62995 to strengthen the definitions of the reduction intrinsics by letting the scalar result/accumulator type be overloaded from the vector element type. For example: ; The LLVM LangRef specifies that the scalar result must equal the ; vector element type, but this is not checked/enforced by LLVM. declare i32 @llvm.experimental.vector.reduce.or.i32.v4i32(<4 x i32> %a) This patch changes that into: declare i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32> %a) Which has the type-constraint more explicit and causes LLVM to check the result type with the vector element type. Reviewers: RKSimon, arsenm, rnk, greened, aemerson Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D62996 llvm-svn: 363240
* [IntrinsicEmitter] Extend argument overloading with forward references.Sander de Smalen2019-06-132-23/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extend the mechanism to overload intrinsic arguments by using either backward or forward references to the overloadable arguments. In for example: def int_something : Intrinsic<[LLVMPointerToElt<0>], [llvm_anyvector_ty], []>; LLVMPointerToElt<0> is a forward reference to the overloadable operand of type 'llvm_anyvector_ty' and would allow intrinsics such as: declare i32* @llvm.something.v4i32(<4 x i32>); declare i64* @llvm.something.v2i64(<2 x i64>); where the result pointer type is deduced from the element type of the first argument. If the returned pointer is not a pointer to the element type, LLVM will give an error: Intrinsic has incorrect return type! i64* (<4 x i32>)* @llvm.something.v4i32 Reviewers: RKSimon, arsenm, rnk, greened Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D62995 llvm-svn: 363233
* [RISCV] Replace map with set in getReqFeaturesSameer AbuAsal2019-06-101-9/+7
| | | | | | | | | | | | | | | | | | | | Summary: Use a set in getReqFeatures() in RISCVCompressInstEmitter instead of a map because the index we save is not needed. This also fixes bug 41666. Reviewers: llvm-commits, apazos, asb, nickdesaulniers Reviewed By: asb Subscribers: Jim, nickdesaulniers, rbar, johnrusso, simoncook, niosHD, kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna Tags: #llvm Differential Revision: https://reviews.llvm.org/D61412 llvm-svn: 362968
* Allow target to handle STRICT floating-point nodesUlrich Weigand2019-06-053-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ISD::STRICT_ nodes used to implement the constrained floating-point intrinsics are currently never passed to the target back-end, which makes it impossible to handle them correctly (e.g. mark instructions are depending on a floating-point status and control register, or mark instructions as possibly trapping). This patch allows the target to use setOperationAction to switch the action on ISD::STRICT_ nodes to Legal. If this is done, the SelectionDAG common code will stop converting the STRICT nodes to regular floating-point nodes, but instead pass the STRICT nodes to the target using normal SelectionDAG matching rules. To avoid having the back-end duplicate all the floating-point instruction patterns to handle both strict and non-strict variants, we make the MI codegen explicitly aware of the floating-point exceptions by introducing two new concepts: - A new MCID flag "mayRaiseFPException" that the target should set on any instruction that possibly can raise FP exception according to the architecture definition. - A new MI flag FPExcept that CodeGen/SelectionDAG will set on any MI instruction resulting from expansion of any constrained FP intrinsic. Any MI instruction that is *both* marked as mayRaiseFPException *and* FPExcept then needs to be considered as raising exceptions by MI-level codegen (e.g. scheduling). Setting those two new flags is straightforward. The mayRaiseFPException flag is simply set via TableGen by marking all relevant instruction patterns in the .td files. The FPExcept flag is set in SDNodeFlags when creating the STRICT_ nodes in the SelectionDAG, and gets inherited in the MachineSDNode nodes created from it during instruction selection. The flag is then transfered to an MIFlag when creating the MI from the MachineSDNode. This is handled just like fast-math flags like no-nans are handled today. This patch includes both common code changes required to implement the new features, and the SystemZ implementation. Reviewed By: andrew.w.kaylor Differential Revision: https://reviews.llvm.org/D55506 llvm-svn: 362663
* [TableGen] Fix std::array initializer to avoid warnings with older tool ↵Mikael Holmen2019-06-031-1/+1
| | | | | | | | | | | | | chains. NFC A std::array is implemented as a template with an array inside a struct. Older versions of clang, like 3.6, require an extra set of curly braces around std::array initializations to avoid warnings. The C++ language was changed regarding this by CWG 1270. So more modern tool chains does not complain even if leaving out one level of braces. llvm-svn: 362360
* [X86] Make the X86FoldTablesEmitter functional again. Fix the spacing in the ↵Craig Topper2019-06-011-24/+37
| | | | | | | | | output to make it easier to diff. Fix a few other formatting issues in the manual table. And remove some old FIXMEs. llvm-svn: 362287
* Follow up and fix for rL362064Sjoerd Meijer2019-05-311-1/+2
| | | | | | | | Fix the misleadingly indentation introduced in rL362064. This will get rid of the compiler warning, and it was actually a bug. This change will be used and tested in D62669. llvm-svn: 362211
* [X86] Add VP2INTERSECT instructionsPengfei Wang2019-05-311-0/+20
| | | | | | | | | | Support Intel AVX512 VP2INTERSECT instructions in llvm Patch by Xiang Zhang (xiangzhangllvm) Differential Revision: https://reviews.llvm.org/D62366 llvm-svn: 362188
* [TableGen] AsmMatcher: allow repeated input operandsSjoerd Meijer2019-05-301-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | If an assembly instruction has to mention an input operand name twice, for example the MVE VMOV instruction that accesses two lanes of the same vector by writing 'vmov r1, r2, q0[3], q0[1]', then the obvious way to write its AsmString is to include the same operand (here $Qd) twice. But this causes the AsmMatcher generator to omit that instruction completely from the match table, on the basis that the generator isn't clever enough to deal with the duplication. But you need to have _some_ way of dealing with an instruction like this - and in this case, where the mnemonic is shared with many other instructions that the AsmMatcher does handle, it would be very painful to take it out of the AsmMatcher system completely. A nicer way is to add a custom AsmMatchConverter routine, and let that deal with the problem if the autogenerated converter can't. But that doesn't work, because TableGen leaves the instruction out of its table _even_ if you provide a custom converter. Solution: this change, which makes TableGen relax the restriction on duplicated operands in the case where there's a custom converter. Patch by: Simon Tatham Differential Revision: https://reviews.llvm.org/D60695 llvm-svn: 362066
* [TableGen] New default operand "undef_tied_input"Sjoerd Meijer2019-05-303-5/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | This is a new special identifier which you can use as a default in OperandWithDefaultOps. The idea is that you use it for an input operand of an instruction that's tied to an output operand, and its semantics are that (in the default case) the input operand's value is not used at all. The detailed effect is that when instruction selection emits the instruction in the form of a pre-regalloc MachineInstr, it creates an IMPLICIT_DEF node to use as that input. If you're creating an MCInst with explicit register names, then the right handling would be to set the input operand to the same register as the output one (honouring the tie) and to add the 'undef' flag indicating that that register is deemed to acquire a new don't-care definition just before we read it. But I haven't done that in this commit, because there was no need to - no Tablegen backend seems to autogenerate default fields in an MCInst. Patch by: Simon Tatham Differential Revision: https://reviews.llvm.org/D60696 llvm-svn: 362064
* [TableGen] - Type comparison LE should be LT or equal.Pete Couperus2019-05-201-11/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D61705 llvm-svn: 361183
* [AMDGPU] gfx1010 SearchableTableEmitter patch for NSAStanislav Mekhanoshin2019-05-131-1/+1
| | | | | | | | This part was accidentally missing from NSA image support commit. Differential Revision: https://reviews.llvm.org/D61868 llvm-svn: 360623
* Revert "[TableGen] Fix a typo"Krasimir Georgiev2019-05-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This reverts commit r360106. The revisioin causes llvm-tblgen to hang while generating info for RISCV.td. The root cause might be in the RISCV.td definition but I don't know enough about this to investigate further. Command that starts hangning after r360106: `llvm-build/bin/llvm-tblgen -I llvm/include -I llvm/tools/clang/include -I llvm/lib/Target/RISCV -gen-instr-info llvm/lib/Target/RISCV/RISCV.td` Reviewers: sammccall, yan_luo, craig.topper, gribozavr Reviewed By: gribozavr Subscribers: PkmX, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D61632 llvm-svn: 360136
* [TableGen] Fix a typoYan Luo2019-05-071-1/+1
| | | | | | | | Check "Big" instead of "Small" in the second condition. Differential Revision: https://reviews.llvm.org/D61605 llvm-svn: 360106
* [TableGen] Fix null pointer dereferencing.Simon Pilgrim2019-04-291-1/+1
| | | | | | Reported in https://www.viva64.com/en/b/0629/ llvm-svn: 359474
* Use llvm::stable_sortFangrui Song2019-04-234-17/+15
| | | | | | While touching the code, simplify if feasible. llvm-svn: 358996
* [TableGen] Include schedule model name in diagnostic.Simon Tatham2019-04-151-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | If you have more than one schedule model in your TableGen target definitions, then the diagnostic "No schedule information for instruction 'foo'" is rather unhelpful, because it doesn't tell you _which_ schedule model is missing the necessary information (or, as it might be, missing the UnsupportedFeatures definition that would stop it thinking it needed it). Extended the message to include the name of the schedule model that it's complaining about. Reviewers: nhaehnle, hfinkel, javedabsar, efriedma, javed.absar Reviewed By: javed.absar Subscribers: javed.absar, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60559 llvm-svn: 358389
* [X86] Remove check on isAsmParserOnly from EVEX2VEX tablegenerator. NFCICraig Topper2019-04-091-3/+1
| | | | | | There are no instructions VEX or EVEX instructions that set this field. llvm-svn: 357973
* [X86] Have EVEX2VEX tablegenerator use HasVEX_L and HasEVEX_L2 fields ↵Craig Topper2019-04-091-32/+8
| | | | | | | | | | instead of the composite EVEX_LL field. Remove the EVEX_LL field. NFCI The composite existed to simplify some other tablegen code and not really in an important way. Remove the combined field and just calculate the vector size using two ifs. llvm-svn: 357972
* [X86] Use VEX_WIG for VPINSRB/W and VPEXTRB/W to match what is done for EVEX.Craig Topper2019-04-091-1/+1
| | | | | | | | | | | | | The instruction's document this as W0 for the VEX encoding. But there's a footnote mentioning that VEX.W is ignored in 64-bit mode. And the main VEX encoding description says the VEX.W bit is ignored for instructions that are equivalent to a legacy SSE instruction that uses REX.W to select a GPR which would apply here. By making this match EVEX we can remove a special case of allowing EVEX2VEX to turn an EVEX.WIG instruction into VEX.W0. llvm-svn: 357971
* [X86] Split the VEX_WPrefix in X86Inst tablegen class into 3 separate fields ↵Craig Topper2019-04-093-32/+23
| | | | | | with clear meanings. llvm-svn: 357970
* [X86] Merge the different Jcc instructions for each condition code into ↵Craig Topper2019-04-052-1/+10
| | | | | | | | | | | | | | | | | | | | | single instructions that store the condition code as an operand. Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon Reviewed By: RKSimon Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60228 llvm-svn: 357802
* [X86] Merge the different SETcc instructions for each condition code into ↵Craig Topper2019-04-052-3/+18
| | | | | | | | | | | | | | | | | | | | | single instructions that store the condition code as an operand. Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between SETcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: andreadb, courbet, RKSimon, spatel, lebedev.ri Reviewed By: andreadb Subscribers: hiraditya, lebedev.ri, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60138 llvm-svn: 357801
* [X86] Merge the different CMOV instructions for each condition code into ↵Craig Topper2019-04-052-5/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | single instructions that store the condition code as an immediate. Summary: Reorder the condition code enum to match their encodings. Move it to MC layer so it can be used by the scheduler models. This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between CMOV instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. This does complicate the scheduler models a little since we can't assign the A and BE instructions to a separate class now. I plan to make similar changes for SETcc and Jcc. Reviewers: RKSimon, spatel, lebedev.ri, andreadb, courbet Reviewed By: RKSimon Subscribers: gchatelet, hiraditya, kristina, lebedev.ri, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60041 llvm-svn: 357800
* [TableGen] Properly calculate the minimum size needed or ConvertFn in ↵Craig Topper2019-04-021-7/+11
| | | | | | | | | | GenAsmmatcher.inc files We were using the number of Matchables rather than the number of rows in the converter table. This only matters for a few of the targets where the number of matchables is more than 255, but the number of converters is less than 255. Many of the targets have more than 256 converters. So already required a uint16_t. llvm-svn: 357527
* fix typo: "\t" => " "Liang Zou2019-03-311-1/+1
| | | | | | | | | | | | | | Reviewers: llvm.org, Jim Reviewed By: Jim Subscribers: arsenm, jvesely, nhaehnle, rupprecht, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59983 llvm-svn: 357365
* [WebAssembly] Merge used feature sets, update atomics linkage policyThomas Lively2019-03-291-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: It does not currently make sense to use WebAssembly features in some functions but not others, so this CL adds an IR pass that takes the union of all used feature sets and applies it to each function in the module. This allows us to prevent atomics from being lowered away if some function has opted in to using them. When atomics is not enabled anywhere, we detect whether there exists any atomic operations or thread local storage that would be stripped and disallow linking with objects that contain atomics if and only if atomics or tls are stripped. When atomics is enabled, mark it as used but do not require it of other objects in the link. These changes allow libraries that do not use atomics to be built once and linked into both single-threaded and multithreaded binaries. Reviewers: aheejin, sbc100, dschuff Subscribers: jgravelle-google, hiraditya, sunfish, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59625 llvm-svn: 357226
* [X86] Allow any 8-bit immediate to be used with BT/BTC/BTR/BTS not just sign ↵Craig Topper2019-03-181-0/+6
| | | | | | | | extended 8-bit immediates. We need to allow [128,255] in addition to [-128, 127] to match gas. llvm-svn: 356413
* [X86] Remove the _alt forms of (V)CMP instructions. Use a combination of ↵Craig Topper2019-03-181-4/+0
| | | | | | | | | | custom printing and custom parsing to achieve the same result and more Similar to previous change done for VPCOM and VPCMP Differential Revision: https://reviews.llvm.org/D59468 llvm-svn: 356384
* [X86] Add ADD8ri_DB and ADD8rr_DB to the autogenerated load folding table.Craig Topper2019-03-181-0/+3
| | | | | | | | | These were added in r355423. We only use the autogenerated table to assist with the maintenance of the manual table. These entries are alreayd in the manual table. llvm-svn: 356357
* [CodeGen] Defined MVTs v3i32, v3f32, v5i32, v5f32Tim Renouf2019-03-171-0/+4
| | | | | | | | | AMDGPU would like to use these MVTs. Differential Revision: https://reviews.llvm.org/D58901 Change-Id: I6125fea810d7cc62a4b4de3d9904255a1233ae4e llvm-svn: 356351
* [X86] Remove the _alt forms of AVX512 VPCMP instructions. Use a combination ↵Craig Topper2019-03-171-2/+0
| | | | | | | | | | of custom printing and custom parsing to achieve the same result and more Similar to the previous patch for VPCOM. Differential Revision: https://reviews.llvm.org/D59398 llvm-svn: 356344
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