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| author | Craig Topper <craig.topper@intel.com> | 2019-04-05 19:28:09 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-04-05 19:28:09 +0000 |
| commit | 80aa2290fb02386579e5d7b0a1d8ce3691fd88da (patch) | |
| tree | 1978efce308a80e3eb9b48155418940531556fb2 /llvm/utils/TableGen | |
| parent | 7323c2bf850b61b85252e17e6f1f73037c328378 (diff) | |
| download | bcm5719-llvm-80aa2290fb02386579e5d7b0a1d8ce3691fd88da.tar.gz bcm5719-llvm-80aa2290fb02386579e5d7b0a1d8ce3691fd88da.zip | |
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon
Reviewed By: RKSimon
Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60228
llvm-svn: 357802
Diffstat (limited to 'llvm/utils/TableGen')
| -rw-r--r-- | llvm/utils/TableGen/X86RecognizableInstr.cpp | 10 | ||||
| -rw-r--r-- | llvm/utils/TableGen/X86RecognizableInstr.h | 1 |
2 files changed, 10 insertions, 1 deletions
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp index 716631e4cb2..6f0f1b950b2 100644 --- a/llvm/utils/TableGen/X86RecognizableInstr.cpp +++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp @@ -495,6 +495,13 @@ void RecognizableInstr::emitInstructionSpecifier() { HANDLE_OPERAND(opcodeModifier) HANDLE_OPTIONAL(relocation) break; + case X86Local::AddCCFrm: + // Operand 1 (optional) is an address or immediate. + assert(numPhysicalOperands == 2 && + "Unexpected number of operands for AddCCFrm"); + HANDLE_OPERAND(relocation) + HANDLE_OPERAND(opcodeModifier) + break; case X86Local::MRMDestReg: // Operand 1 is a register operand in the R/M field. // - In AVX512 there may be a mask operand here - @@ -749,6 +756,7 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { case X86Local::RawFrmDstSrc: case X86Local::RawFrmImm8: case X86Local::RawFrmImm16: + case X86Local::AddCCFrm: filter = llvm::make_unique<DumbFilter>(); break; case X86Local::MRMDestReg: @@ -800,7 +808,7 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { if (Form == X86Local::AddRegFrm || Form == X86Local::MRMSrcRegCC || Form == X86Local::MRMSrcMemCC || Form == X86Local::MRMXrCC || - Form == X86Local::MRMXmCC) { + Form == X86Local::MRMXmCC || Form == X86Local::AddCCFrm) { unsigned Count = Form == X86Local::AddRegFrm ? 8 : 16; assert(((opcodeToSet % Count) == 0) && "ADDREG_FRM opcode not aligned"); diff --git a/llvm/utils/TableGen/X86RecognizableInstr.h b/llvm/utils/TableGen/X86RecognizableInstr.h index 0a31e42ea4e..bb535d231e6 100644 --- a/llvm/utils/TableGen/X86RecognizableInstr.h +++ b/llvm/utils/TableGen/X86RecognizableInstr.h @@ -101,6 +101,7 @@ namespace X86Local { RawFrmDstSrc = 6, RawFrmImm8 = 7, RawFrmImm16 = 8, + AddCCFrm = 9, MRMDestMem = 32, MRMSrcMem = 33, MRMSrcMem4VOp3 = 34, |
