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* This patch fixes a problem encountered by the CellSPU backend where variantsScott Michel2008-03-052-53/+132
| | | | | | | | | | | | | | were being pruned in patterns where a variable was used more than once, e.g.: (or (and R32C:$rA, R32C:$rC), (and R32C:$rB, (not R32C:$rC))) In this example, $rC is used more than once and is actually significant to instruction selection pattern matching when commuted variants are produced. This patch scans the pattern's clauses and collects the variables, creating a set of variables that are used more than once. TreePatternNode::isIsomorphicTo() also understands that multiply-used variables are significant. llvm-svn: 47950
* Rename PrintableName to Name.Bill Wendling2008-02-261-4/+4
| | | | llvm-svn: 47629
* Change "Name" to "AsmName" in the target register info. Gee, a refactoring toolBill Wendling2008-02-261-2/+2
| | | | | | would have been a Godsend here! llvm-svn: 47625
* De-tabify.Bill Wendling2008-02-262-19/+19
| | | | llvm-svn: 47595
* Some platforms use the same name for 32-bit and 64-bit registers (likeBill Wendling2008-02-241-1/+11
| | | | | | | | | %r3 on PPC) in their ASM files. However, it's hard for humans to read during debugging. Adding a new field to the register data that lets you specify a different name to be printed than the one that goes into the ASM file -- %x3 instead of %r3, for instance. llvm-svn: 47534
* Unbreak build with gcc 4.3: provide missed includes and silence most ↵Anton Korobeynikov2008-02-205-5/+10
| | | | | | annoying warnings. llvm-svn: 47367
* Make tblgen a little smarter about constants smaller than i32. Currently,Scott Michel2008-02-152-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | tblgen will complain if a sign-extended constant does not fit into a data type smaller than i32, e.g., i16. This causes a problem when certain hex constants are used, such as 0xff for byte masks or immediate xor values. tblgen will try the sign-extended value first and, if the sign extended value would overflow, it tries to see if the unsigned value will fit. Consequently, a software developer can now safely incant: (XORHIr16 R16C:$rA, 0xffff) which is somewhat clearer and more informative than incanting: (XORHIr16 R16C:$rA, (i16 -1)) even if the two are bitwise equivalent. Tblgen also outputs the 64-bit unsigned constant in the generated ISel code when getTargetConstant() is invoked. llvm-svn: 47188
* Rewrite tblgen handling of subtarget features soDale Johannesen2008-02-141-2/+6
| | | | | | | | | | it follows the order of the enum, not alphabetical. The motivation is to make -mattr=+ssse3,+sse41 select SSE41 as it ought to. Added "ignored" enum values of 0 to PPC and SPU to avoid compiler warnings. llvm-svn: 47143
* Change how FP immediates are handled. Nate Begeman2008-02-141-0/+13
| | | | | | | | | | | | | | 1) ConstantFP is now expand by default 2) ConstantFP is not turned into TargetConstantFP during Legalize if it is legal. This allows ConstantFP to be handled like Constant, allowing for targets that can encode FP immediates as MachineOperands. As a bonus, fix up Itanium FP constants, which now correctly match, and match more constants! Hooray. llvm-svn: 47121
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-3/+3
| | | | llvm-svn: 46930
* Tablegen support for insert & extract element matchingNate Begeman2008-02-092-1/+22
| | | | llvm-svn: 46901
* Re-apply the memory operand changes, with a fix for the staticDan Gohman2008-02-061-0/+28
| | | | | | | | initializer problem, a minor tweak to the way the DAGISelEmitter finds load/store nodes, and a renaming of the new PseudoSourceValue objects. llvm-svn: 46827
* Fix PR1975: dag isel emitter produces patterns that isel wrong flag result.Evan Cheng2008-02-051-4/+21
| | | | llvm-svn: 46776
* Dwarf requires variable entries to be in the source order. Right now, since ↵Evan Cheng2008-02-041-3/+0
| | | | | | we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead. llvm-svn: 46724
* Change the 'global modification' APIs in SelectionDAG to take a newChris Lattner2008-02-031-22/+35
| | | | | | | | | | DAGUpdateListener object pointer instead of just returning a vector of deleted nodes. This makes the interfaces more efficient (no more allocating a vector [at least a malloc], filling it in, then walking it) and more clean. This also allows the client to be notified of nodes that are *changed* but not deleted. llvm-svn: 46677
* Get rid of the annoying blank lines before labels.Evan Cheng2008-02-021-0/+3
| | | | llvm-svn: 46667
* SDIsel processes llvm.dbg.declare by recording the variable debug ↵Evan Cheng2008-02-025-0/+38
| | | | | | | | | information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc. Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes. For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time. llvm-svn: 46659
* Revert 46556 and 46585. Dan please fix the PseudoSourceValue problem and ↵Evan Cheng2008-01-311-27/+0
| | | | | | re-commit. llvm-svn: 46623
* Add an extra operand to LABEL nodes which distinguishes between debug, EH, ↵Evan Cheng2008-01-311-4/+7
| | | | | | or misc labels. This fixes the EH breakage. However I am not convinced this is *the* solution. llvm-svn: 46609
* Allow ComplexExpressions in InstrInfo.td files to be slightly more... ↵Christopher Lamb2008-01-313-6/+28
| | | | | | | | | | complex! ComplexExpressions can now have attributes which affect how TableGen interprets the pattern when generating matchin code. The first (and currently, only) attribute causes the immediate parent node of the ComplexPattern operand to be passed into the matching code rather than the node at the root of the entire DAG containing the pattern. llvm-svn: 46606
* Create a new class, MemOperand, for describing memory referencesDan Gohman2008-01-311-0/+27
| | | | | | | | | | | | | | | | in the backend. Introduce a new SDNode type, MemOperandSDNode, for holding a MemOperand in the SelectionDAG IR, and add a MemOperand list to MachineInstr, and code to manage them. Remove the offset field from SrcValueSDNode; uses of SrcValueSDNode that were using it are all all using MemOperandSDNode now. Also, begin updating some getLoad and getStore calls to use the PseudoSourceValue objects. Most of this was written by Florian Brander, some reorganization and updating to TOT by me. llvm-svn: 46585
* Fix to bug 1951: tblgen gratuitously renames variables when no temporary wasScott Michel2008-01-291-22/+26
| | | | | | | | | | | | | | | | | | | | | | | | | generated. This feature would only show up in fairly complex patterns, such as this one in CellSPU: def : Pat<(add (SPUhi tconstpool:$in, 0), (SPUlo tconstpool:$in, 0)), (IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in)>; which generated the following emit code: SDNode *Emit_0(const SDOperand &N, unsigned Opc0, unsigned Opc1, MVT::ValueType VT0, MVT::ValueType VT1) DISABLE_INLINE { SDOperand N0 = N.getOperand(0); SDOperand N00 = N0.getOperand(0); SDOperand N01 = N0.getOperand(1); SDOperand N1 = N.getOperand(1); SDOperand N10 = N1.getOperand(0); SDOperand N11 = N1.getOperand(1); SDOperand Tmp3(CurDAG->getTargetNode(Opc0, VT0, N00), 0); return CurDAG->SelectNodeTo(N.Val, Opc1, VT1, Tmp3, Tmp2); /* Tmp2 s/b N00 */ } Tested against the test suites without incident. llvm-svn: 46487
* Add interator interface to DAGInit alsoAnton Korobeynikov2008-01-221-0/+22
| | | | llvm-svn: 46250
* Provide iterator access to ListInit contentsAnton Korobeynikov2008-01-211-0/+11
| | | | llvm-svn: 46223
* Add files to windows project files. Also include <algorithm> explicitly so ↵Chuck Rose III2008-01-151-0/+1
| | | | | | that vstudio build works llvm-svn: 46013
* Rename CCIfStruct to CCIfByVal and CCStructAssign to CCPassByVal. Remove ↵Evan Cheng2008-01-151-3/+6
| | | | | | unused parameters of CCStructAssign and add size and alignment requirement info. llvm-svn: 45997
* Revert my last commit. Not needed.Evan Cheng2008-01-151-20/+7
| | | | llvm-svn: 45994
* ByVal arguments are passed on stack. Make sure to allocate a slot using size ↵Evan Cheng2008-01-121-7/+20
| | | | | | and alignment information on the parameter attribute. llvm-svn: 45897
* Simplify the side effect stuff a bit more and make licm/sinkingChris Lattner2008-01-101-2/+1
| | | | | | | | | | | | | | | | both work right according to the new flags. This removes the TII::isReallySideEffectFree predicate, and adds TII::isInvariantLoad. It removes NeverHasSideEffects+MayHaveSideEffects and adds UnmodeledSideEffects as machine instr flags. Now the clients can decide everything they need. I think isRematerializable can be implemented in terms of the flags we have now, though I will let others tackle that. llvm-svn: 45843
* Start inferring side effect information more aggressively, and fix many bugs ↵Chris Lattner2008-01-104-27/+43
| | | | | | | | | | | | | | in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
* Fix a crash on code like: let x = 1 {xChris Lattner2008-01-101-1/+4
| | | | llvm-svn: 45827
* if an instr lacks a pattern, assume it has side effects (unless never has ↵Chris Lattner2008-01-101-1/+4
| | | | | | s-e is true). llvm-svn: 45823
* start inferring 'no side effects'.Chris Lattner2008-01-104-56/+62
| | | | llvm-svn: 45822
* Infer mayloadChris Lattner2008-01-101-3/+13
| | | | llvm-svn: 45819
* realize that instructions who match intrinsics that read memory read memory.Chris Lattner2008-01-103-3/+15
| | | | | | Also, instructions with any nodes that are SDNPMayLoad also read memory. llvm-svn: 45817
* add a mayLoad property for machine instructions, a correlary to mayStore.Chris Lattner2008-01-083-13/+14
| | | | | | This is currently not set by anything. llvm-svn: 45748
* rename TargetInstrDescriptor -> TargetInstrDesc.Chris Lattner2008-01-071-2/+2
| | | | | | | Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
* Rename all the M_* flags to be namespace qualified enums, and switch Chris Lattner2008-01-071-25/+25
| | | | | | | | all clients over to using predicates instead of these flags directly. These are now private values which are only to be used to statically initialize the tables. llvm-svn: 45692
* rename hasVariableOperands() -> isVariadic(). Add some comments.Chris Lattner2008-01-074-7/+7
| | | | | | | Evan, please review the comments I added to getNumDefs to make sure that they are accurate, thx. llvm-svn: 45687
* Move M_* flags down in the file. Move SchedClass up in the Chris Lattner2008-01-071-2/+2
| | | | | | | TargetInstrDescriptor class and shrink to 16-bits, saving a word in TargetInstrDescriptor. Add some comments. llvm-svn: 45686
* the name field of instructions is never set to a non-empty string, Chris Lattner2008-01-073-17/+3
| | | | | | just unconditionally use the def name of the instruction. llvm-svn: 45684
* Add predicates methods to TargetOperandInfo, and switch all clients Chris Lattner2008-01-071-3/+3
| | | | | | | over to using them, instead of diddling Flags directly. Change the various flags from const variables to enums. llvm-svn: 45677
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-063-4/+4
| | | | llvm-svn: 45667
* rename isStore -> mayStore to more accurately reflect what it captures.Chris Lattner2008-01-063-18/+19
| | | | llvm-svn: 45656
* Change the 'isStore' inferrer to look for 'SDNPMayStore' Chris Lattner2008-01-063-12/+33
| | | | | | | | | | | instead of "ISD::STORE". This allows us to mark target-specific dag nodes as storing (such as ppc byteswap stores). This allows us to remove more explicit isStore flags from the .td files. Finally, add a warning for when a .td file contains an explicit isStore and tblgen is able to infer it. llvm-svn: 45654
* set the 'isstore' flag for instructions whose pattern is an Chris Lattner2008-01-063-14/+35
| | | | | | intrinsic that writes to memory. llvm-svn: 45650
* remove some old hacky code that tried to infer whether a store Chris Lattner2008-01-062-20/+50
| | | | | | | | | | | occured in a pattern, but failed miserably. The new code works for any instruction that has a store in its pattern, including all the x86 mem op mem instructions. The only target-independent code that uses this is branch folding, so this won't change anything in practice. llvm-svn: 45648
* rearrange some code to allow inferring instr info from the pattern of the ↵Chris Lattner2008-01-062-34/+56
| | | | | | instr, but don't do so yet. llvm-svn: 45647
* improve const correctness.Chris Lattner2008-01-063-3/+3
| | | | llvm-svn: 45646
* Split the impl of CodeGenInstruction out to its own .cpp file, add a ↵Chris Lattner2008-01-063-265/+287
| | | | | | getName() accessor. llvm-svn: 45645
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