| Commit message (Collapse) | Author | Age | Files | Lines |
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particularly on X86 where AVX instructions just add a 'v' to the front of other instructions.
llvm-svn: 153841
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search to do the lookup.
This also avoids emitting the information twice, which led to code bloat. On i386-linux-Release+Asserts
with all targets built this change shaves a whopping 1.3 MB off clang. The number is probably exaggerated
by recent inliner changes but the methods were already enormous with the old inline cost computation.
The DWARF reg -> LLVM reg mapping doesn't seem to have holes in it, so it could be a simple lookup table.
I didn't implement that optimization yet to avoid potentially changing functionality.
There is still some duplication both in tablegen and the generated code that should be cleaned up eventually.
llvm-svn: 153837
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llvm-svn: 153796
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First small step toward modeling multi-register multi-pressure. In the
future, register units can also be used to model liveness and
aliasing.
llvm-svn: 153794
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It's slow, bloated and completely redundant with MCRegisterClass::contains.
llvm-svn: 153782
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This allows suffix sharing in register names. (AX is a suffix of EAX).
llvm-svn: 153777
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Use an explicit comparator instead of the default.
The sets are sorted, but not using the default comparator. Hopefully,
this will unbreak the Linux builders.
llvm-svn: 153772
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--enable-expensive-checks build.
llvm-svn: 153771
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Many register classes have the same value types. Share the table space.
llvm-svn: 153764
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TableGen emits lists of sub-registers, super-registers, and overlaps. Put
them all in a single table and use a SequenceToOffsetTable to share
suffixes.
llvm-svn: 153761
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This is similar to the StringToOffsetTable we use to produce string
tables, but it can be used for other sequences than strings, and it
eliminates entries for suffixes.
llvm-svn: 153760
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llvm-svn: 153667
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The arm_neon intrinsics can create virtual registers from the DPair
register class which allows both even-odd and odd-even D-register pairs.
This fixes PR12389.
llvm-svn: 153603
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llvm-svn: 153457
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was the c backend.
llvm-svn: 153432
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through StringExtras.h
llvm-svn: 153328
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llvm-svn: 153125
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llvm-svn: 152906
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reference instead of value to avoid some copying.
llvm-svn: 152899
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the opening parenthese instead of 2 spaces in.
llvm-svn: 152889
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same result could be found with VariableInstructions.size(). Also fix some typos in comments.
llvm-svn: 152885
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llvm-svn: 152840
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We currently assume that all targets have less than 64k opcodes. We
shouldn't limit it further.
llvm-svn: 152833
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We cannot limit the concatenated instruction names to 64K. ARM is
already at 32K, and it is easy to imagine a target with more
instructions.
llvm-svn: 152817
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This patch limited the concatenated register names to 64K which meant
that the total number of registers was many times less than 64K.
If any compilers actually enforce the 64K limit on string literals, and
it turns out to be a problem, we should fix that problem by not using
long string literals.
llvm-svn: 152816
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declaration from class to run method since its only used there and was being reinitialized anyway.
llvm-svn: 152616
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llvm-svn: 152581
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uint16_t to reduce space.
llvm-svn: 152538
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reduce size of static tables.
llvm-svn: 152524
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prefix. Added a FIXME to remind us this still does not work when it is not the
first prefix.
llvm-svn: 152414
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~0U might be i32 on 32-bit hosts, then (uint64_t)~0U might not be expected as (i64)0xFFFFFFFF_FFFFFFFF, but as (i64)0x00000000_FFFFFFFF.
llvm-svn: 152407
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llvm-svn: 152301
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Original commit message:
Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect all 16-bit string table offsets. Also make sure the string to offset table string is not larger than 65536 characters since larger string literals aren't portable.
llvm-svn: 152296
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Original commit message:
Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect
all 16-bit string table offsets. Also make sure the string to offset table
string is not larger than 65536 characters since larger string literals aren't
portable.
llvm-svn: 152233
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protect all 16-bit string table offsets. Also make sure the string to offset table string is not larger than 65536 characters since larger string literals aren't portable.
llvm-svn: 152202
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Register pair, all lanes subscripting.
llvm-svn: 152157
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Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.
llvm-svn: 152150
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truncating them to 32-bits prior to this.
llvm-svn: 152148
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string literals so the index into the big string can never be larger than that.
llvm-svn: 152105
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llvm-svn: 152104
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llvm-svn: 152067
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Use the new composite physical registers.
llvm-svn: 152063
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With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.
llvm-svn: 152045
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llvm-svn: 152019
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static data size.
llvm-svn: 152016
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llvm-svn: 152001
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static data size.
llvm-svn: 151998
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size of static data.
llvm-svn: 151996
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Shaves 150k off the size of X86DisassemblerDecoder.o
llvm-svn: 151995
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llvm-svn: 151986
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