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* Replace ValueTypes.h with MachineValueType.h if possible.Patrik Hagglund2014-03-154-4/+4
| | | | | | | | | Utilize the previous move of MVT to a separate header for all trivial cases (that don't need any further restructuring). Reviewed By: Tim Northover llvm-svn: 204003
* [TableGen] Optionally forbid overlap between named and positional operandsHal Finkel2014-03-132-3/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are currently two schemes for mapping instruction operands to instruction-format variables for generating the instruction encoders and decoders for the assembler and disassembler respectively: a) to map by name and b) to map by position. In the long run, we'd like to remove the position-based scheme and use only name-based mapping. Unfortunately, the name-based scheme currently cannot deal with complex operands (those with suboperands), and so we currently must use the position-based scheme for those. On the other hand, the position-based scheme cannot deal with (register) variables that are split into multiple ranges. An upcoming commit to the PowerPC backend (adding VSX support) will require this capability. While we could teach the position-based scheme to handle that, since we'd like to move away from the position-based mapping generally, it seems silly to teach it new tricks now. What makes more sense is to allow for partial transitioning: use the name-based mapping when possible, and only use the position-based scheme when necessary. Now the problem is that mixing the two sensibly was not possible: the position-based mapping would map based on position, but would not skip those variables that were mapped by name. Instead, the two sets of assignments would overlap. However, I cannot currently change the current behavior, because there are some backends that rely on it [I think mistakenly, but I'll send a message to llvmdev about that]. So I've added a new TableGen bit variable: noNamedPositionallyEncodedOperands, that can be used to cause the position-based mapping to skip variables mapped by name. llvm-svn: 203767
* Fix a false error reported by the tblgen backend for machine modelAndrew Trick2014-03-131-0/+12
| | | | | | | | | "ProcResource def is not included in the ProcResources". Some of the machine model definitions were not added to the processor's list used for diagnostics and error checking. llvm-svn: 203749
* Remove copy ctors that did the same thing as the default one.Benjamin Kramer2014-03-111-5/+0
| | | | | | | The code added nothing but potentially disabled move semantics and made types non-trivially copyable. llvm-svn: 203563
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-091-2/+2
| | | | | | class. llvm-svn: 203418
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-093-22/+23
| | | | | | class. llvm-svn: 203378
* Replace PROLOG_LABEL with a new CFI_INSTRUCTION.Rafael Espindola2014-03-072-2/+3
| | | | | | | | | | | | | | | | | | | | | | | The old system was fairly convoluted: * A temporary label was created. * A single PROLOG_LABEL was created with it. * A few MCCFIInstructions were created with the same label. The semantics were that the cfi instructions were mapped to the PROLOG_LABEL via the temporary label. The output position was that of the PROLOG_LABEL. The temporary label itself was used only for doing the mapping. The new CFI_INSTRUCTION has a 1:1 mapping to MCCFIInstructions and points to one by holding an index into the CFI instructions of this function. I did consider removing MMI.getFrameInstructions completelly and having CFI_INSTRUCTION own a MCCFIInstruction, but MCCFIInstructions have non trivial constructors and destructors and are somewhat big, so the this setup is probably better. The net result is that we don't create temporary labels that are never used. llvm-svn: 203204
* clang-format a bit of code to make the next patch easier to read.Rafael Espindola2014-03-071-21/+5
| | | | llvm-svn: 203203
* AVX-512: Added rrk, rrkz, rmk, rmkz, rmbk, rmbkz versions of AVX512 FP ↵Elena Demikhovsky2014-03-061-0/+2
| | | | | | | | packed instructions, added encoding tests for them. By Robert Khazanov. llvm-svn: 203098
* Replace OwningPtr<T> with std::unique_ptr<T>.Ahmed Charles2014-03-063-14/+12
| | | | | | | | | | This compiles with no changes to clang/lld/lldb with MSVC and includes overloads to various functions which are used by those projects and llvm which have OwningPtr's as parameters. This should allow out of tree projects some time to move. There are also no changes to libs/Target, which should help out of tree targets have time to move, if necessary. llvm-svn: 203083
* [C++11] Replace OwningPtr::take() with OwningPtr::release().Ahmed Charles2014-03-053-12/+12
| | | | llvm-svn: 202957
* [C++11] Add 'override' keywords to tablegen code.Craig Topper2014-03-055-172/+167
| | | | llvm-svn: 202937
* [cleanup] Re-sort all the includes with utils/sort_includes.py.Chandler Carruth2014-03-041-1/+1
| | | | llvm-svn: 202811
* [C++11] Use std::tie to simplify compare operators.Benjamin Kramer2014-03-031-5/+2
| | | | | | No functionality change. llvm-svn: 202751
* Unbreak the C++11 build.Benjamin Kramer2014-03-031-1/+1
| | | | llvm-svn: 202714
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-021-4/+4
| | | | | | Remove the old functions. llvm-svn: 202636
* Now that we have C++11, turn simple functors into lambdas and remove a ton ↵Benjamin Kramer2014-03-014-51/+14
| | | | | | | | of boilerplate. No intended functionality change. llvm-svn: 202588
* Add an OutPatFrag TableGen classHal Finkel2014-02-282-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unfortunately, it is currently impossible to use a PatFrag as part of an output pattern (the part of the pattern that has instructions in it) in TableGen. Looking at the current implementation, this was clearly intended to work (there is already code in place to expand patterns in the output DAG), but is currently broken by the baked-in type-checking assumption and the order in which the pattern fragments are processed (output pattern fragments need to be processed after the instruction definitions are processed). Fixing this is fairly simple, but requires some way of differentiating output patterns from the existing input patterns. The simplest way to handle this seems to be to create a subclass of PatFrag, and so that's what I've done here. As a simple example, this allows us to write: def crnot : OutPatFrag<(ops node:$in), (CRNOR $in, $in)>; def : Pat<(not i1:$in), (crnot $in)>; which captures the core use case: handling of repeated subexpressions inside of complicated output patterns. This will be used by an upcoming commit to the PowerPC backend. llvm-svn: 202450
* Fix indentation.Craig Topper2014-02-271-1/+1
| | | | llvm-svn: 202344
* [x86] Simplify disassembler code slightly.Craig Topper2014-02-261-4/+4
| | | | llvm-svn: 202233
* Stackmaps are used for OSR exits, which is a custom kind of unwinding. ↵Filip Pizlo2014-02-201-0/+1
| | | | | | | | | | | | | | | | | Hence, they should not be marked nounwind. Marking them nounwind caused crashes in the WebKit FTL JIT, because if we enable sufficient optimizations, LLVM starts eliding compact_unwind sections (or any unwind data for that matter), making deoptimization via stackmaps impossible. This changes the stackmap intrinsic to be may-throw, adds a test for exactly the sympton that WebKit saw, and fixes TableGen to handle un-attributed intrinsics. Thanks to atrick and philipreames for reviewing this. llvm-svn: 201826
* [x86] Switch PAUSE instruction to use XS prefix instead of HasREPPrefix. ↵Craig Topper2014-02-202-4/+1
| | | | | | Remove HasREPPrefix support from disassembler table generator since its now only used by CodeGenOnly instructions. llvm-svn: 201767
* Remove special FP opcode maps and instead add enough MRM_XX formats to ↵Craig Topper2014-02-191-47/+46
| | | | | | handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change. llvm-svn: 201649
* Put some of the X86 formats in a more logical order.Craig Topper2014-02-191-20/+20
| | | | llvm-svn: 201645
* Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of ↵Craig Topper2014-02-193-20/+14
| | | | | | 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. llvm-svn: 201641
* Rename a DebugLoc variable to DbgLoc and a DataLayout to DL.Rafael Espindola2014-02-181-2/+2
| | | | | | This is quiet a bit less confusing now that TargetData was renamed DataLayout. llvm-svn: 201606
* Add an x86 prefix encoding for instructions that would decode to a different ↵Craig Topper2014-02-181-10/+38
| | | | | | instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
* Remove unused method declaration.Craig Topper2014-02-131-3/+0
| | | | llvm-svn: 201301
* Remove filtering concept from X86 disassembler table generation. It's no ↵Craig Topper2014-02-134-73/+15
| | | | | | longer necessary. llvm-svn: 201299
* Remove special case filtering for instructions with lock prefix as they are ↵Craig Topper2014-02-122-8/+0
| | | | | | all marked with isCodeGenOnly already. llvm-svn: 201216
* Mark XACQUIRE_PREFIX/XRELEASE_PREFIX as isAsmParserOnly so they'll disappear ↵Craig Topper2014-02-121-6/+0
| | | | | | from the disassembler table build without custom filtering code. llvm-svn: 201215
* Recommit r201059 and r201060 with hopefully a fix for its original failure.Craig Topper2014-02-101-299/+40
| | | | | | | | | | Original commits messages: Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code. Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information. llvm-svn: 201065
* Revert r201059 and r201060.Bob Wilson2014-02-101-40/+299
| | | | | | | | r201059 appears to cause a crash in a bootstrapped build of clang. Craig isn't available to look at it right now, so I'm reverting it while he investigates. llvm-svn: 201064
* Simplify a bunch of code by removing the need for the x86 disassembler table ↵Craig Topper2014-02-101-301/+36
| | | | | | builder to know about extended opcodes. The modrm forms are sufficient to convey the information. llvm-svn: 201060
* Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' ↵Craig Topper2014-02-101-0/+6
| | | | | | field of modrm byte as a don't care value. Will allow for simplification of disassembler code. llvm-svn: 201059
* Remove unnecessary include.Craig Topper2014-02-093-3/+0
| | | | llvm-svn: 201041
* Remove some unnecessary code. The conditions it was checking had already ↵Craig Topper2014-02-091-7/+0
| | | | | | been ruled out by the caller. llvm-svn: 201039
* LLVM-1163: AAPCS-VFP violation when CPRC allocated to stackOliver Stannard2014-02-071-2/+24
| | | | | | | | | | | | According to the AAPCS, when a CPRC is allocated to the stack, all other VFP registers should be marked as unavailable. I have also modified the rules for allocating non-CPRCs to the stack, to make it more explicit that all GPRs must be made unavailable. I cannot think of a case where the old version would produce incorrect answers, so there is no test for this. llvm-svn: 200970
* Delete all of the CodeGenInstructions from CodeGenTarget destructor.Craig Topper2014-02-061-0/+1
| | | | llvm-svn: 200906
* Shrink the size of CodeGenInstruction a little bit by using bitfields. 32 ↵Craig Topper2014-02-052-36/+39
| | | | | | bools seemed excessive. llvm-svn: 200829
* Get rid of a vector copy by just making a pointer out of the reference ↵Craig Topper2014-02-051-15/+15
| | | | | | returned by getInstructionsByEnumValue instead of assigning it to a new vector. llvm-svn: 200828
* Fix a vector that was passed by value instead of reference.Craig Topper2014-02-051-5/+5
| | | | llvm-svn: 200827
* Fix a doxygen comment referencing the wrong method name.Craig Topper2014-02-051-2/+2
| | | | llvm-svn: 200825
* Add CheckChildInteger to ISelMatcher operations. Removes nearly 2000 bytes ↵Craig Topper2014-02-054-1/+61
| | | | | | from X86 matcher table. llvm-svn: 200821
* TableGen/X86RecognizableInstr.h: Prune out-of-date "@param isSSE". ↵NAKAMURA Takumi2014-02-021-4/+0
| | | | | | [-Wdocumentation] llvm-svn: 200628
* Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 ↵Craig Topper2014-02-022-77/+71
| | | | | | meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
* Simplify some code since VEX and EVEX instructions never have HasOpSizePrefix.Craig Topper2014-02-021-10/+10
| | | | llvm-svn: 200625
* Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field ↵Craig Topper2014-02-022-28/+29
| | | | | | in TSFlags. llvm-svn: 200624
* Separate x86 opcode maps and 0x66/0xf2/0xf3 prefixes from each other in the ↵Craig Topper2014-01-312-123/+73
| | | | | | TSFlags. This greatly simplifies the switch statements in the disassembler tables and the code emitters. llvm-svn: 200522
* Move REP out of the Prefix field of the X86 format. Give it its own bit. It ↵Craig Topper2014-01-312-3/+4
| | | | | | had special handling anyway and this enables a future patch. llvm-svn: 200520
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