Fix a false error reported by the tblgen backend for machine model

"ProcResource def is not included in the ProcResources".

Some of the machine model definitions were not added to the
processor's list used for diagnostics and error checking.

llvm-svn: 203749

1 files changed, 12 insertions, 0 deletions

diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp
index c84fe6d82d7..a07524d76be 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -1473,11 +1473,23 @@ void CodeGenSchedModels::collectProcResources() {
     Record *ModelDef = (*WRI)->getValueAsDef("SchedModel");
     addWriteRes(*WRI, getProcModel(ModelDef).Index);
   }
+  RecVec SWRDefs = Records.getAllDerivedDefinitions("SchedWriteRes");
+  for (RecIter WRI = SWRDefs.begin(), WRE = SWRDefs.end(); WRI != WRE; ++WRI) {
+    Record *ModelDef = (*WRI)->getValueAsDef("SchedModel");
+    addWriteRes(*WRI, getProcModel(ModelDef).Index);
+  }
   RecVec RADefs = Records.getAllDerivedDefinitions("ReadAdvance");
   for (RecIter RAI = RADefs.begin(), RAE = RADefs.end(); RAI != RAE; ++RAI) {
     Record *ModelDef = (*RAI)->getValueAsDef("SchedModel");
     addReadAdvance(*RAI, getProcModel(ModelDef).Index);
   }
+  RecVec SRADefs = Records.getAllDerivedDefinitions("SchedReadAdvance");
+  for (RecIter RAI = SRADefs.begin(), RAE = SRADefs.end(); RAI != RAE; ++RAI) {
+    if ((*RAI)->getValueInit("SchedModel")->isComplete()) {
+      Record *ModelDef = (*RAI)->getValueAsDef("SchedModel");
+      addReadAdvance(*RAI, getProcModel(ModelDef).Index);
+    }
+  }
   // Add ProcResGroups that are defined within this processor model, which may
   // not be directly referenced but may directly specify a buffer size.
   RecVec ProcResGroups = Records.getAllDerivedDefinitions("ProcResGroup");