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* AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmpElena Demikhovsky2014-01-012-43/+50
| | | | | | | Printing rounding control. Enncoding for EVEX_RC (rounding control). llvm-svn: 198277
* Second attempt at Removing special form of AddRegFrm used by FP ↵Craig Topper2014-01-013-51/+25
| | | | | | instructions. These instructions can be handled by MRMXr instead. llvm-svn: 198276
* Revert r198238 and add FP disassembler tests. It didn't work and I didn't ↵Craig Topper2013-12-313-25/+51
| | | | | | realized we had no FP disassembler test cases. llvm-svn: 198265
* Remove special form of AddRegFrm used by FP instructions. These instructions ↵Craig Topper2013-12-303-51/+25
| | | | | | can be handled by MRMXr instead. llvm-svn: 198238
* Remove EscapeFilter. It's funcionality can be covered by correctly using ↵Craig Topper2013-12-303-33/+15
| | | | | | ExtendedFilter and ExactFilter. No functional change. llvm-svn: 198226
* Simplify filter accepts function to just return 'condition' instead of ↵Craig Topper2013-12-301-28/+13
| | | | | | branching to return true/false. No functional change. llvm-svn: 198221
* AVX-512: decoder for AVX-512, made by Alexey Bader.Elena Demikhovsky2013-12-251-4/+26
| | | | llvm-svn: 198013
* [x86] Rename In32BitMode predicate to Not64BitModeEric Christopher2013-12-201-2/+3
| | | | | | | | | | | That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse llvm-svn: 197768
* Add support for positionally-encoded operands to FixedLenDecoderEmitterHal Finkel2013-12-191-4/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unfortunately, the PowerPC instruction definitions make heavy use of the positional operand encoding heuristic to map operands onto bitfield variables in the instruction definitions. Changing this to use name-based mapping is not trivial, however, because additional infrastructure needs to be designed to handle mapping of complex operands (with multiple suboperands) onto multiple bitfield variables. In the mean time, this adds support for positionally encoded operands to FixedLenDecoderEmitter, so that we can generate a disassembler for the PowerPC backend. To prevent an accidental reliance on this feature, and to prevent an undesirable interaction with existing disassemblers, a backend must opt-in to this support by setting the new decodePositionallyEncodedOperands instruction-set bit to true. When enabled, this iterates the variables that contribute to the instruction encoding, just as the encoder does, and emulates the procedure the encoder uses to map "numbered" operands to variables. The bit range for each variable is also determined as the encoder determines them. This map is then consulted during the decoder-generator's loop over operands to decode, allowing the decoder to understand both position-based and name-based operand-to-variable mappings. As noted in the comment on the decodePositionallyEncodedOperands definition, this support should be removed once it is no longer needed. There should be no change to existing disassemblers. llvm-svn: 197691
* Add support for PointerLikeRegClass to FixedLenDecoderEmitterHal Finkel2013-12-191-0/+4
| | | | | | | | This is more prep for adding the PowerPC disassembler. FixedLenDecoderEmitter should recognize PointerLikeRegClass operands as register types, and generate register-like decoding calls instead of treating them like immediates. llvm-svn: 197680
* Support little-endian encodings in the FixedLenDecoderEmitterHal Finkel2013-12-174-37/+47
| | | | | | | | | | | | | | | The convention used to specify the PowerPC ISA is that bits are numbered in reverse order (0 is the index of the high bit). To support this "little endian" encoding convention, CodeEmitterGen will reverse the bit numberings prior to generating the encoding tables. In order to generate a disassembler, FixedLenDecoderEmitter needs to do the same. This moves the bit reversal logic out of CodeEmitterGen and into CodeGenTarget (where it can be used by both CodeEmitterGen and FixedLenDecoderEmitter). This is prep work for disassembly support in the PPC backend (which is the only in-tree user of this little-endian encoding support). llvm-svn: 197532
* AVX-512: Added legal type MVT::i1 and VK1 register for it.Elena Demikhovsky2013-12-161-0/+7
| | | | | | | | | Added scalar compare VCMPSS, VCMPSD. Implemented LowerSELECT for scalar FP operations. I replaced FSETCCss, FSETCCsd with one node type FSETCCs. Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1. llvm-svn: 197384
* Correct word hyphenationsAlp Toker2013-12-051-1/+1
| | | | | | | This patch tries to avoid unrelated changes other than fixing a few hyphen-related ambiguities and contractions in nearby lines. llvm-svn: 196471
* Remove dead code.Rafael Espindola2013-12-023-35/+2
| | | | llvm-svn: 196066
* [weak vtables] Place class definitions into anonymous namespaces to prevent ↵Juergen Ributzka2013-11-192-45/+33
| | | | | | | | | | weak vtables. This patch places class definitions in implementation files into anonymous namespaces to prevent weak vtables. This eliminates the need of providing an out-of-line definition to pin the vtable explicitly to the file. llvm-svn: 195092
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-194-58/+86
| | | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. The memory leaks in this version have been fixed. Thanks Alexey for pointing them out. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 195064
* Revert r194865 and r194874.Alexey Samsonov2013-11-184-83/+58
| | | | | | | | | | | | This change is incorrect. If you delete virtual destructor of both a base class and a subclass, then the following code: Base *foo = new Child(); delete foo; will not cause the destructor for members of Child class. As a result, I observe plently of memory leaks. Notable examples I investigated are: ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl. llvm-svn: 194997
* TableGen: Generate an enum for all named Operand types in tblgen'd InstrInfo.Ahmed Bougacha2013-11-171-0/+31
| | | | llvm-svn: 194978
* Small improvement to InstrinsicEmitter::EmitAttributes. This change removes ↵Owen Anderson2013-11-161-17/+38
| | | | | | | | the “pushing” and “clearing” of the SmallVector and instead uses const arrays to pass the attributeKinds to AttributeSet::get . Patch by Aditya Nandakumar. llvm-svn: 194899
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-154-58/+83
| | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 194865
* AVX-512: added VPCONFLICT instruction and intrinsics,Elena Demikhovsky2013-11-033-5/+39
| | | | | | added EVEX_KZ to tablegen llvm-svn: 193959
* Lower stackmap intrinsics directly to their target opcode in the DAG builder.Andrew Trick2013-10-311-0/+2
| | | | llvm-svn: 193769
* Enable variable arguments support for intrinsics.Andrew Trick2013-10-311-1/+4
| | | | llvm-svn: 193766
* whitespaceAndrew Trick2013-10-311-49/+49
| | | | llvm-svn: 193765
* TableGen: remove unused variable.Ahmed Bougacha2013-10-281-0/+1
| | | | llvm-svn: 193527
* TableGen: Refactor DAG patterns to enable parsing one pattern at a time.Ahmed Bougacha2013-10-282-51/+65
| | | | llvm-svn: 193526
* TableGen: Refactor AsmWriterEmitter to keep AsmWriterInsts.Ahmed Bougacha2013-10-281-26/+26
| | | | | | | | These used to be referenced by the CGI->AWI map (in AsmWriterEmitter), but stored in a vector local to EmitPrintInstruction. Move the vector to AsmWriterEmitter too. llvm-svn: 193525
* Typo.Peter Collingbourne2013-10-201-1/+1
| | | | llvm-svn: 193043
* Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps ↵Craig Topper2013-10-141-0/+3
| | | | | | instructions to parse either GR32 or GR64 without resorting to duplicating instructions. llvm-svn: 192567
* Remove more filters from the disassembler. Mark some AVX512 instructions as ↵Craig Topper2013-10-121-5/+0
| | | | | | CodeGenOnly. llvm-svn: 192525
* Mark some more instructions as CodeGenOnly. Remove filters from the ↵Craig Topper2013-10-121-4/+0
| | | | | | disassembler. llvm-svn: 192522
* Add missing #include's to cctype when using isdigit/alpha/etc.Will Dietz2013-10-121-0/+1
| | | | llvm-svn: 192519
* Remove another unnecessary filter from the disassembler.Craig Topper2013-10-111-3/+0
| | | | llvm-svn: 192425
* Fix so CRC32r64r8 isn't accidentally filtered from the disassembler tables.Craig Topper2013-10-101-1/+1
| | | | llvm-svn: 192339
* More x86 disassembler filtering cleanup.Craig Topper2013-10-091-4/+1
| | | | llvm-svn: 192279
* Remove some old filters from the x86 disassembler table builder.Craig Topper2013-10-091-6/+0
| | | | llvm-svn: 192275
* Remove unneeded MMX instruction definition by moving pattern to an ↵Craig Topper2013-10-081-1/+0
| | | | | | equivalent instruction definition and removing the filtering from the disassembler table building. llvm-svn: 192175
* Remove some instructions that existed to provide aliases to the assembler. ↵Craig Topper2013-10-081-3/+1
| | | | | | Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. llvm-svn: 192171
* Remove some instructions that seem to only exist to trick the filtering ↵Craig Topper2013-10-071-1/+2
| | | | | | checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead. llvm-svn: 192090
* Add disassembler support for long encodings for INC/DEC in 32-bit mode.Craig Topper2013-10-071-1/+2
| | | | llvm-svn: 192086
* Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences ↵Craig Topper2013-10-054-1/+46
| | | | | | of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon. llvm-svn: 192026
* Revert r191940 to see if it fixes the build bots.Craig Topper2013-10-044-46/+1
| | | | llvm-svn: 191941
* Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences ↵Craig Topper2013-10-044-1/+46
| | | | | | of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon. llvm-svn: 191940
* Add XOP disassembler support. Fixes PR13933.Craig Topper2013-10-033-3/+72
| | | | llvm-svn: 191874
* Add v4f16 to supported value types.Pete Cooper2013-10-031-0/+1
| | | | | | This is useful for some ARM intrinsics such as VCVTN which does a <4 x float> <-> <4 x half> conversion. llvm-svn: 191870
* Remove several unused variables.Rafael Espindola2013-10-014-12/+0
| | | | | | Patch by Alp Toker. llvm-svn: 191757
* Fix pattern sort in DAGISelEmitter.cppRichard Sandiford2013-10-011-9/+7
| | | | | | | The old code skipped one of the sorting criteria if either pattern had no types. This could lead to cycles of the form X < Y, Y < Z, Z < X. llvm-svn: 191735
* Filter out repeated sections from the X86 disassembler modRMTable. Saves ↵Craig Topper2013-09-302-87/+67
| | | | | | about ~43K from a released build. Unfortunately the disassembler tables are still upwards of 800K. llvm-svn: 191652
* Various x86 disassembler fixes.Craig Topper2013-09-301-6/+18
| | | | | | | | | | | Add VEX_LIG to scalar FMA4 instructions. Use VEX_LIG in some of the inheriting checks in disassembler table generator. Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts. Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set. Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases. Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms. llvm-svn: 191649
* Mark the x86 machine model as incomplete. PR17367.Andrew Trick2013-09-251-0/+5
| | | | | | | | | | | | Ideally, the machinel model is added at the time the instructions are defined. But many instructions in X86InstrSSE.td still need a model. Without this workaround the scheduler asserts because x86 already has itinerary classes for these instructions, indicating they should be modeled by the scheduler. Since we use the new machine model for other instructions, it expects a new machine model for these too. llvm-svn: 191391
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