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| author | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2013-12-16 13:52:35 +0000 |
|---|---|---|
| committer | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2013-12-16 13:52:35 +0000 |
| commit | 47fc44e52e8e7bad1b901bfae4dc78dec048d5f1 (patch) | |
| tree | 8586cd784e15966833f1fd058be7c214a290f4d2 /llvm/utils/TableGen | |
| parent | 43fc44007db9a503acf0a1787405baf334d35b1e (diff) | |
| download | bcm5719-llvm-47fc44e52e8e7bad1b901bfae4dc78dec048d5f1.tar.gz bcm5719-llvm-47fc44e52e8e7bad1b901bfae4dc78dec048d5f1.zip | |
AVX-512: Added legal type MVT::i1 and VK1 register for it.
Added scalar compare VCMPSS, VCMPSD.
Implemented LowerSELECT for scalar FP operations.
I replaced FSETCCss, FSETCCsd with one node type FSETCCs.
Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1.
llvm-svn: 197384
Diffstat (limited to 'llvm/utils/TableGen')
| -rw-r--r-- | llvm/utils/TableGen/X86RecognizableInstr.cpp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp index 708e72d36e1..6b5123a4963 100644 --- a/llvm/utils/TableGen/X86RecognizableInstr.cpp +++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp @@ -1269,6 +1269,8 @@ OperandType RecognizableInstr::typeFromString(const std::string &s, TYPE("VR256", TYPE_XMM256) TYPE("VR256X", TYPE_XMM256) TYPE("VR512", TYPE_XMM512) + TYPE("VK1", TYPE_VK1) + TYPE("VK1WM", TYPE_VK1) TYPE("VK8", TYPE_VK8) TYPE("VK8WM", TYPE_VK8) TYPE("VK16", TYPE_VK16) @@ -1340,6 +1342,7 @@ OperandEncoding RecognizableInstr::rmRegisterEncodingFromString ENCODING("VR256", ENCODING_RM) ENCODING("VR256X", ENCODING_RM) ENCODING("VR512", ENCODING_RM) + ENCODING("VK1", ENCODING_RM) ENCODING("VK8", ENCODING_RM) ENCODING("VK16", ENCODING_RM) errs() << "Unhandled R/M register encoding " << s << "\n"; @@ -1367,8 +1370,10 @@ OperandEncoding RecognizableInstr::roRegisterEncodingFromString ENCODING("FR64X", ENCODING_REG) ENCODING("FR32X", ENCODING_REG) ENCODING("VR512", ENCODING_REG) + ENCODING("VK1", ENCODING_REG) ENCODING("VK8", ENCODING_REG) ENCODING("VK16", ENCODING_REG) + ENCODING("VK1WM", ENCODING_REG) ENCODING("VK8WM", ENCODING_REG) ENCODING("VK16WM", ENCODING_REG) errs() << "Unhandled reg/opcode register encoding " << s << "\n"; @@ -1389,6 +1394,7 @@ OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString ENCODING("VR128X", ENCODING_VVVV) ENCODING("VR256X", ENCODING_VVVV) ENCODING("VR512", ENCODING_VVVV) + ENCODING("VK1", ENCODING_VVVV) ENCODING("VK8", ENCODING_VVVV) ENCODING("VK16", ENCODING_VVVV) errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; @@ -1398,6 +1404,7 @@ OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString (const std::string &s, bool hasOpSizePrefix) { + ENCODING("VK1WM", ENCODING_WRITEMASK) ENCODING("VK8WM", ENCODING_WRITEMASK) ENCODING("VK16WM", ENCODING_WRITEMASK) errs() << "Unhandled mask register encoding " << s << "\n"; |
