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* [TableGen] Ensure proper ordering of subtarget feature namesKrzysztof Parzyszek2017-03-061-4/+17
| | | | llvm-svn: 297039
* Fixed IntOperandMatcher::emitCxxPredicateExpr argumentsSimon Pilgrim2017-02-241-1/+1
| | | | | | Extra const in the StringRef argument meant that MSVC complained about it not correctly overriding from OperandPredicateMatcher::emitCxxPredicateExpr (which didn't have the const) llvm-svn: 296138
* [globalisel] Decouple src pattern operands from dst pattern operands.Daniel Sanders2017-02-241-53/+282
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This isn't testable for AArch64 by itself so this patch also adds support for constant immediates in the pattern and physical register uses in the result. The new IntOperandMatcher matches the constant in patterns such as '(set $rd:GPR32, (G_XOR $rs:GPR32, -1))'. It's always safe to fold immediates into an instruction so this is the first rule that will match across multiple BB's. The Renderer hierarchy is responsible for adding operands to the result instruction. Renderers can copy operands (CopyRenderer) or add physical registers (in particular %wzr and %xzr) to the result instruction in any order (OperandMatchers now import the operand names from SelectionDAG to allow renderers to access any operand). This allows us to emit the result instruction for: %1 = G_XOR %0, -1 --> %1 = ORNWrr %wzr, %0 %1 = G_XOR -1, %0 --> %1 = ORNWrr %wzr, %0 although the latter is untested since the matcher/importer has not been taught about commutativity yet. Added BuildMIAction which can build new instructions and mutate them where possible. W.r.t the mutation aspect, MatchActions are now told the name of an instruction they can recycle and BuildMIAction will emit mutation code when the renderers are appropriate. They are appropriate when all operands are rendered using CopyRenderer and the indices are the same as the matcher. This currently assumes that all operands have at least one matcher. Finally, this change also fixes a crash in AArch64InstructionSelector::select() caused by an immediate operand passing isImm() rather than isCImm(). This was uncovered by the other changes and was detected by existing tests. Depends on D29711 Reviewers: t.p.northover, ab, qcolombet, rovka, aditya_nandakumar, javed.absar Reviewed By: rovka Subscribers: aemerson, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29712 llvm-svn: 296131
* Fix missing call to base class constructor in r296121.Daniel Sanders2017-02-241-1/+3
| | | | | | | The 'Kind' member used in RTTI for InstructionPredicateMatcher was not initialized but went undetected since I always ended up with the correct value. llvm-svn: 296126
* [globalisel] Sort RuleMatchers by priority.Daniel Sanders2017-02-241-2/+165
| | | | | | | | | | | | | | | | | | | | | | Summary: This makes more important rules have priority over less important rules. For example, '%a = G_ADD $b:s64, $c:s64' has priority over '%a = G_ADD $b:s32, $c:s32'. Previously these rules were emitted in the correct order by chance. NFC in this patch but it is required to make the next patch work correctly. Depends on D29710 Reviewers: t.p.northover, ab, qcolombet, aditya_nandakumar, rovka Reviewed By: ab, rovka Subscribers: javed.absar, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D29711 llvm-svn: 296121
* tablegen: Fix android buildPavel Labath2017-02-211-1/+2
| | | | | | use llvm::to_string instead of std:: version. llvm-svn: 295711
* Add a wrapper around copy_if in STLExtras; NFCSanjoy Das2017-02-211-4/+3
| | | | | | I will add one more use for this in a later change. llvm-svn: 295685
* [globalisel] OperandPredicateMatcher's shouldn't need to generate the ↵Daniel Sanders2017-02-201-17/+18
| | | | | | | | | | | | | | | | | | | | | | | | MachineOperand expr. NFC Summary: Each OperandPredicateMatcher shouldn't need to know how to generate the expression to reference a MachineOperand. The OperandMatcher should provide it. In addition to separating responsibilities, this also lays some groundwork for decoupling source patterns from destination patterns to allow invented operands or operands provided by GlobalISel's equivalent to the ComplexPattern<> class. Depends on D29709 Reviewers: t.p.northover, ab, rovka, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: dberris, kristof.beyls, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D29710 llvm-svn: 295668
* [globalisel] Separate the SelectionDAG importer from the emitter. NFCDaniel Sanders2017-02-201-5/+11
| | | | | | | | | | | | | | | | Summary: In the near future the rules will be sorted between these two steps to ensure that more important rules are not prevented by less important ones. Reviewers: t.p.northover, ab, rovka, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29709 llvm-svn: 295661
* [X86][AVX] Extend hasVEX_WPrefix bit to accept WIG value (W Ignore) + update ↵Ayman Musa2017-02-202-11/+15
| | | | | | | | | | | all AVX instructions with the new value. Add WIG value to all of AVX instructions which ignore the W-bit in their encoding, instead of giving them the default value of 0. This patch is needed for a follow up work on EVEX2VEX pass (replacing EVEX encoded instructions with their corresponding VEX version when possible). Differential Revision: https://reviews.llvm.org/D29876 llvm-svn: 295643
* [TableGen] Make sure EnforceSameSize populates the type sets if necessary.Craig Topper2017-02-181-0/+6
| | | | | | This was found by another commit I'm working on. llvm-svn: 295578
* [Tablegen] Instrumenting table gen DAGGenISelDAGAditya Nandakumar2017-02-141-4/+135
| | | | | | | | | | To help assist in debugging ISEL or to prioritize GlobalISel backend work, this patch adds two more tables to <Target>GenISelDAGISel.inc - one which contains the patterns that are used during selection and the other containing include source location of the patterns Enabled through CMake varialbe LLVM_ENABLE_DAGISEL_COV llvm-svn: 295081
* [GlobalISel] Return an Expected<RuleMatcher> for each SDAG pattern. NFC.Ahmed Bougacha2017-02-101-55/+63
| | | | | | | | | | | | | | Instead of emitting the matcher code directly, return the rule matcher and the skip reason as an Expected<RuleMatcher>. This will let us record all matchers and process them before emission. It's a somewhat unconventional use of Error, but it's nicer than, say, std::pair, because of the bool conversions. Differential Revision: https://reviews.llvm.org/D29743 llvm-svn: 294706
* [TableGen][AsmWriterEmitter] Use a deterministic order to sort InstrAliasesQuentin Colombet2017-02-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Inside an alias group, when ordering instruction aliases, we rely on the priority field to sort them. When the priority is not set or more generally when there is a tie between two aliases, we used to rely on the lexicographic order. However, this order can change for the anonymous records when more instruction, intrinsic, etc. are inserted. For instance, given two anonymous records r1 and r2 with respective name A_999 and A_1000, their lexicography order will be r2 then r1. Now, if an instruction is added before them, their name will become respectively A_1000 and A_1001, thus the lexicography order will be r1 then r2, i.e., it changed. If that happens in an alias group, the assembly output would prefer a different alias for no apparent good reasons. A way to fix that is to use proper priority for all aliases, but we can also make the tie breaker comparison smarter and use a deterministic ordering. This is what this patch does. llvm-svn: 294695
* [GlobalISel] Simplify StringRef parameters. NFC.Ahmed Bougacha2017-02-091-9/+8
| | | | | | 'const' on StringRef parameters adds no guarantees. Remove it. llvm-svn: 294555
* Revert r294437 as it broke an asan buildbot.Amara Emerson2017-02-081-7/+2
| | | | llvm-svn: 294523
* [AArch64][TableGen] Skip tied result operands for InstAliasAmara Emerson2017-02-081-2/+7
| | | | | | | | | | | | | | | | | | | | | | | This patch checks the number of operands in the resulting instruction instead of just the alias, then skips over tied operands when generating the printing method. This allows us to generate the preferred assembly syntax for the AArch64 'ins' instruction, which should always be displayed as 'mov' according to the ARMARM. Several unit tests have changed as a result, but only to reflect the preferred disassembly. Some other InstAlias patterns (movk/bic/orr) needed a slight adjustment to stop them becoming the default and breaking other unit tests. Patch by Graham Hunter. Differential Revision: https://reviews.llvm.org/D29219 llvm-svn: 294437
* Move mnemonicIsValid to Mips target.Craig Topper2017-02-081-24/+0
| | | | | | | | | | | | | | | | | | | | Summary: The Mips target is the only user of mnemonicIsValid. This patch moves this method from AsmMatcherEmitter.cpp to MipsAsmParser.cpp, getting rid of the method in all other targets where it generated warnings about an unused function. Patch by Gonsolo. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: sdardis Differential Revision: https://reviews.llvm.org/D28748 llvm-svn: 294400
* [TableGen] Use less stack in DAGISelMatcherOptJon Chesterfield2017-02-061-9/+15
| | | | | | | | Refactor a helper function, FactorNodes, to search for a push node in constant space. This resolves a problem in a not-yet-upstreamed backend where a recursive pattern blew the call stack (at a depth of 255) under a debug build of tablegen. No functional change so no new test coverage. The change is minimal to avoid disturbing existing behaviour. Differential Revision: https://reviews.llvm.org/D29080 llvm-svn: 294230
* [GlobalISel] Add a few comments to the tablegen backend. NFC.Ahmed Bougacha2017-02-041-4/+14
| | | | | | Based on a review of D29478 by Kristof Beyls. llvm-svn: 294077
* [GlobalISel] Print the matched patterns using an action.Ahmed Bougacha2017-02-041-8/+16
| | | | | | | | This lets us split out PatternToMatch from the top-level RuleMatcher, where it doesn't really belong. That, in turn, lets us eventually generate RuleMatchers from non-SelectionDAG sources. llvm-svn: 294076
* [GlobalISel] Separate matchers with newlines in emitted selector. NFC.Ahmed Bougacha2017-02-041-4/+4
| | | | | | | We don't try very hard to format the emitted code, but newlines are an easy way to make it more readable. llvm-svn: 294074
* [globalisel] Fix missing break.Daniel Sanders2017-02-031-0/+1
| | | | | | The instruction selector has been emitting the register bank information too. llvm-svn: 294007
* [globalisel] Make the MatchAction hierarchy consistent with the matchers. NFC.Daniel Sanders2017-02-011-17/+27
| | | | | | | | | | Reviewers: aditya_nandakumar, rovka, t.p.northover, qcolombet, ab Subscribers: dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D29321 llvm-svn: 293760
* TableGen: use fully qualified name for StringLiteralSaleem Abdulrasool2017-01-311-2/+2
| | | | | | | | | Use the qualified name for StringLiteral (llvm::StringLiteral) when generating the sources. This is needed as the generated files may be used out-of-tree (e.g. swift) where you may not have a `using namespace llvm;` resulting in an undefined lookup. llvm-svn: 293577
* Fix the GCC build.Benjamin Kramer2017-01-301-2/+2
| | | | | | This is fairly ugly, but apparently GCC still doesn't understand C++11. llvm-svn: 293535
* Turn a TableGen FastISelEmitter warning into an error.Michael Kuperstein2017-01-301-7/+4
| | | | | | | | | | | | | Tablegen emitted a warning when the fast isel emitter created dead code by emitting a pattern that has no predicate before a pattern that has one. This should be an error but was originally only a warning because the X86 backend had a buggy definition that unintentionally caused this to be hit (PR21575). That has been fixed a while ago (r222094), so it's safe to upgrade the warning to an error. llvm-svn: 293534
* [IR] Remove global constructor from Function.cppBenjamin Kramer2017-01-301-2/+2
| | | | llvm-svn: 293528
* TableGen: Fix infinite recursion in RegisterBankEmitterTom Stellard2017-01-301-3/+11
| | | | | | | | | | | | | | | | Summary: AMDGPU has two register classes with the same set of registers, and this was causing this tablegen backend would get stuck in infinite recursion. Reviewers: dsanders Reviewed By: dsanders Subscribers: tpr, wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D29049 llvm-svn: 293483
* [globalisel] Rename emitCxxPredicatesExpr() following post-commit review of ↵Daniel Sanders2017-01-281-3/+3
| | | | | | | | r293172 It's now emitCxxPredicateListExpr() to better match the class name. llvm-svn: 293376
* Use print() instead of dump() in codeMatthias Braun2017-01-281-3/+4
| | | | | | | The dump() functions are meant to be used in a debugger, code should typically use something like print(errs()); llvm-svn: 293365
* Cleanup dump() functions.Matthias Braun2017-01-282-4/+4
| | | | | | | | | | | | | | | | | | We had various variants of defining dump() functions in LLVM. Normalize them (this should just consistently implement the things discussed in http://lists.llvm.org/pipermail/cfe-dev/2014-January/034323.html For reference: - Public headers should just declare the dump() method but not use LLVM_DUMP_METHOD or #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) - The definition of a dump method should look like this: #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) LLVM_DUMP_METHOD void MyClass::dump() { // print stuff to dbgs()... } #endif llvm-svn: 293359
* [GlobalISel] Remove duplicate function using variadic templates. NFC.Ahmed Bougacha2017-01-261-21/+5
| | | | | | | | | I think the initial version of r293172 was trying: std::forward<Args...>(args)... which doesn't compile. This seems like the correct way: std::forward<Args>(args)... llvm-svn: 293214
* Remove a '#if 0' that wasn't intended for commit in r293173.Daniel Sanders2017-01-261-19/+0
| | | | | | | The '#if 0' contained the code I had intended to use but clang rejects it (possibly incorrectly). llvm-svn: 293174
* Attempt to fix windows buildbots after r293172.Daniel Sanders2017-01-261-1/+1
| | | | llvm-svn: 293173
* [globalisel] Re-factor ISel matchers into a hierarchy. NFCDaniel Sanders2017-01-261-48/+226
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This should make it possible to easily add everything needed to import all the existing SelectionDAG rules. It should also serve the likely kinds of GlobalISel rules (some of which are not currently representable in SelectionDAG) once we've nailed down the tablegen definition for that. The hierarchy is as follows: MatcherRule - A matching rule. Currently used to emit C++ ISel code but will | also be used to emit test cases and tablegen definitions in the | near future. |- Instruction(s) - Represents the instruction to be matched. |- Instruction Predicate(s) - Test the opcode, arithmetic flags, etc. of an | instruction. \- Operand(s) - Represents a particular operand of the instruction. In the | future, there may be subclasses to test the same predicates | on multiple operands (including for variadic instructions). \ Operand Predicate(s) - Test the type, register bank, etc. of an operand. This is where the ComplexPattern equivalent will be represented. It's also nested-instruction matching will live as a predicate that follows the DefUse chain to the Def and tests a MatcherRule from that position. Support for multiple instruction matchers in a rule has been retained from the existing code but has been adjusted to assert when it is used. Previously it would silently drop all but the first instruction matcher. The tablegen-erated file is not functionally changed but has more parentheses and no longer attempts to format the if-statements since keeping track of the indentation is tricky in the presence of the matcher hierarchy. It would be nice to have CMakes tablegen() run the output through clang-format (when available) so we don't have to complicate TableGen with pretty-printing. It's also worth mentioning that this hierarchy will also be able to emit TableGen definitions and test cases in the near future. This is the reason for favouring explicit emit*() calls rather than the << operator. Reviewers: aditya_nandakumar, rovka, t.p.northover, qcolombet, ab Reviewed By: ab Subscribers: igorb, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D28942 llvm-svn: 293172
* [globalisel] Fix an unused variable warning when NDEBUG is defined.Daniel Sanders2017-01-201-1/+1
| | | | llvm-svn: 292653
* Re-commit: [globalisel] Tablegen-erate current Register Bank InformationDaniel Sanders2017-01-194-1/+320
| | | | | | | | | | | | | | | | | | | | | Summary: Adds a RegisterBank tablegen class that can be used to declare the register banks and an associated tablegen pass to generate the necessary code. Changes since first commit attempt: * Added missing guards * Added more missing guards * Found and fixed a use-after-free bug involving Twine locals Reviewers: t.p.northover, ab, rovka, qcolombet Reviewed By: qcolombet Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka Differential Revision: https://reviews.llvm.org/D27338 llvm-svn: 292478
* Re-revert: [globalisel] Tablegen-erate current Register Bank InformationDaniel Sanders2017-01-184-317/+1
| | | | | | | More missing guards. My build didn't notice it due to a stale file left over from a Global ISel build. llvm-svn: 292369
* Re-commit: [globalisel] Tablegen-erate current Register Bank InformationDaniel Sanders2017-01-184-1/+317
| | | | | | | | | | | | | | | | | | | | | | | Summary: Adds a RegisterBank tablegen class that can be used to declare the register banks and an associated tablegen pass to generate the necessary code. Changes since last commit: The new tablegen pass is now correctly guarded by LLVM_BUILD_GLOBAL_ISEL and this should fix the buildbots however it may not be the whole fix. The previous buildbot failures suggest there may be a memory bug lurking that I'm unable to reproduce (including when using asan) or spot in the source. If they re-occur on this commit then I'll need assistance from the bot owners to track it down. Reviewers: t.p.northover, ab, rovka, qcolombet Reviewed By: qcolombet Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka Differential Revision: https://reviews.llvm.org/D27338 llvm-svn: 292367
* [X86] Fix for bugzilla 31576 - add support for "data32" instruction prefixMarina Yatsina2017-01-181-0/+4
| | | | | | | | | | | This patch fixes bugzilla 31576 (https://llvm.org/bugs/show_bug.cgi?id=31576). "data32" instruction prefix was not defined in the llvm. An exception had to be added to the X86 tablegen and AsmPrinter because both "data16" and "data32" are encoded to 0x66 (but in different modes). Differential Revision: https://reviews.llvm.org/D28468 llvm-svn: 292352
* Revert r292132: [globalisel] Tablegen-erate current Register Bank ↵Daniel Sanders2017-01-164-317/+1
| | | | | | | | | Information'... Several buildbots encountered a crash in tablegen when building this commit. Reverting while I investigate the cause. llvm-svn: 292136
* [globalisel] Tablegen-erate current Register Bank InformationDaniel Sanders2017-01-164-1/+317
| | | | | | | | | | | | | | Summary: Adds a RegisterBank tablegen class that can be used to declare the register banks and an associated tablegen pass to generate the necessary code. Reviewers: t.p.northover, ab, rovka, qcolombet Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka Differential Revision: https://reviews.llvm.org/D27338 llvm-svn: 292132
* [X86] Merge the disassemblers handling of the different TYPE_RELs by getting ↵Craig Topper2017-01-161-6/+6
| | | | | | the size information from the ENCODING field. NFCI llvm-svn: 292096
* [X86] Reduce the number of operand 'types' the disassembler needs to deal ↵Craig Topper2017-01-161-87/+86
| | | | | | | | | with. NFCI We were frequently checking for a list of types and the different types conveyed no real information. So lump them together explicitly. llvm-svn: 292095
* [AVX-512] Begin giving the disassembler a way to recognize that VSIB is a ↵Craig Topper2017-01-161-15/+17
| | | | | | | | different encoding than regular addressing modes. This part first teaches it not to check error if EVEX.V2 is used by a VSIB instruction. llvm-svn: 292093
* [AVX-512] Correct memory operand size for VPGATHERQPS and VPGATHERQDCraig Topper2017-01-161-0/+2
| | | | | | | | | with ZMM index. Similar for SCATTER and the prefetch gather and scatter instructions. Fixes PR31618. llvm-svn: 292088
* Mark comparator call operator as constEric Fiselier2016-12-271-1/+1
| | | | llvm-svn: 290636
* [GlobalISel] Add basic Selector-emitter tblgen backend.Ahmed Bougacha2016-12-215-1/+399
| | | | | | | | | | | | | | | | | This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
* [TableGen] Use 'unsigned' instead of 'bool' in a place where the code ↵Craig Topper2016-12-191-1/+1
| | | | | | conditionally assigns numeric values. They happen to be 0 and 1 so this is NFC. llvm-svn: 290088
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