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authorTom Stellard <thomas.stellard@amd.com>2017-01-30 15:07:01 +0000
committerTom Stellard <thomas.stellard@amd.com>2017-01-30 15:07:01 +0000
commit5b56f2d6cb62feec5864cd16b6001943b35896ad (patch)
tree4794b5e2e3825d896e7783587ad7fa236fa1bdd6 /llvm/utils/TableGen
parent73564981feed86e8638663dff4b9de916d20b97f (diff)
downloadbcm5719-llvm-5b56f2d6cb62feec5864cd16b6001943b35896ad.tar.gz
bcm5719-llvm-5b56f2d6cb62feec5864cd16b6001943b35896ad.zip
TableGen: Fix infinite recursion in RegisterBankEmitter
Summary: AMDGPU has two register classes with the same set of registers, and this was causing this tablegen backend would get stuck in infinite recursion. Reviewers: dsanders Reviewed By: dsanders Subscribers: tpr, wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D29049 llvm-svn: 293483
Diffstat (limited to 'llvm/utils/TableGen')
-rw-r--r--llvm/utils/TableGen/RegisterBankEmitter.cpp14
1 files changed, 11 insertions, 3 deletions
diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index 816fc3e0a17..bf066412b28 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -168,7 +168,14 @@ void RegisterBankEmitter::emitBaseClassDefinition(
static void visitRegisterBankClasses(
CodeGenRegBank &RegisterClassHierarchy, const CodeGenRegisterClass *RC,
const Twine Kind,
- std::function<void(const CodeGenRegisterClass *, StringRef)> VisitFn) {
+ std::function<void(const CodeGenRegisterClass *, StringRef)> VisitFn,
+ SmallPtrSetImpl<const CodeGenRegisterClass *> &VisitedRCs) {
+
+ // Make sure we only visit each class once to avoid infinite loops.
+ if (VisitedRCs.count(RC))
+ return;
+ VisitedRCs.insert(RC);
+
// Visit each explicitly named class.
VisitFn(RC, Kind.str());
@@ -180,7 +187,7 @@ static void visitRegisterBankClasses(
if (RC != &PossibleSubclass && RC->hasSubClass(&PossibleSubclass))
visitRegisterBankClasses(RegisterClassHierarchy, &PossibleSubclass,
TmpKind + " " + RC->getName() + " subclass",
- VisitFn);
+ VisitFn, VisitedRCs);
// Visit each class that contains only subregisters of RC with a common
// subregister-index.
@@ -273,6 +280,7 @@ void RegisterBankEmitter::run(raw_ostream &OS) {
std::vector<RegisterBank> Banks;
for (const auto &V : Records.getAllDerivedDefinitions("RegisterBank")) {
+ SmallPtrSet<const CodeGenRegisterClass *, 8> VisitedRCs;
RegisterBank Bank(*V);
for (const CodeGenRegisterClass *RC :
@@ -282,7 +290,7 @@ void RegisterBankEmitter::run(raw_ostream &OS) {
[&Bank](const CodeGenRegisterClass *RC, StringRef Kind) {
DEBUG(dbgs() << "Added " << RC->getName() << "(" << Kind << ")\n");
Bank.addRegisterClass(RC);
- });
+ }, VisitedRCs);
}
Banks.push_back(Bank);
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