summaryrefslogtreecommitdiffstats
path: root/llvm/utils/TableGen
Commit message (Collapse)AuthorAgeFilesLines
...
* Turn a TableGen FastISelEmitter warning into an error.Michael Kuperstein2017-01-301-7/+4
| | | | | | | | | | | | | Tablegen emitted a warning when the fast isel emitter created dead code by emitting a pattern that has no predicate before a pattern that has one. This should be an error but was originally only a warning because the X86 backend had a buggy definition that unintentionally caused this to be hit (PR21575). That has been fixed a while ago (r222094), so it's safe to upgrade the warning to an error. llvm-svn: 293534
* [IR] Remove global constructor from Function.cppBenjamin Kramer2017-01-301-2/+2
| | | | llvm-svn: 293528
* TableGen: Fix infinite recursion in RegisterBankEmitterTom Stellard2017-01-301-3/+11
| | | | | | | | | | | | | | | | Summary: AMDGPU has two register classes with the same set of registers, and this was causing this tablegen backend would get stuck in infinite recursion. Reviewers: dsanders Reviewed By: dsanders Subscribers: tpr, wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D29049 llvm-svn: 293483
* [globalisel] Rename emitCxxPredicatesExpr() following post-commit review of ↵Daniel Sanders2017-01-281-3/+3
| | | | | | | | r293172 It's now emitCxxPredicateListExpr() to better match the class name. llvm-svn: 293376
* Use print() instead of dump() in codeMatthias Braun2017-01-281-3/+4
| | | | | | | The dump() functions are meant to be used in a debugger, code should typically use something like print(errs()); llvm-svn: 293365
* Cleanup dump() functions.Matthias Braun2017-01-282-4/+4
| | | | | | | | | | | | | | | | | | We had various variants of defining dump() functions in LLVM. Normalize them (this should just consistently implement the things discussed in http://lists.llvm.org/pipermail/cfe-dev/2014-January/034323.html For reference: - Public headers should just declare the dump() method but not use LLVM_DUMP_METHOD or #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) - The definition of a dump method should look like this: #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) LLVM_DUMP_METHOD void MyClass::dump() { // print stuff to dbgs()... } #endif llvm-svn: 293359
* [GlobalISel] Remove duplicate function using variadic templates. NFC.Ahmed Bougacha2017-01-261-21/+5
| | | | | | | | | I think the initial version of r293172 was trying: std::forward<Args...>(args)... which doesn't compile. This seems like the correct way: std::forward<Args>(args)... llvm-svn: 293214
* Remove a '#if 0' that wasn't intended for commit in r293173.Daniel Sanders2017-01-261-19/+0
| | | | | | | The '#if 0' contained the code I had intended to use but clang rejects it (possibly incorrectly). llvm-svn: 293174
* Attempt to fix windows buildbots after r293172.Daniel Sanders2017-01-261-1/+1
| | | | llvm-svn: 293173
* [globalisel] Re-factor ISel matchers into a hierarchy. NFCDaniel Sanders2017-01-261-48/+226
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This should make it possible to easily add everything needed to import all the existing SelectionDAG rules. It should also serve the likely kinds of GlobalISel rules (some of which are not currently representable in SelectionDAG) once we've nailed down the tablegen definition for that. The hierarchy is as follows: MatcherRule - A matching rule. Currently used to emit C++ ISel code but will | also be used to emit test cases and tablegen definitions in the | near future. |- Instruction(s) - Represents the instruction to be matched. |- Instruction Predicate(s) - Test the opcode, arithmetic flags, etc. of an | instruction. \- Operand(s) - Represents a particular operand of the instruction. In the | future, there may be subclasses to test the same predicates | on multiple operands (including for variadic instructions). \ Operand Predicate(s) - Test the type, register bank, etc. of an operand. This is where the ComplexPattern equivalent will be represented. It's also nested-instruction matching will live as a predicate that follows the DefUse chain to the Def and tests a MatcherRule from that position. Support for multiple instruction matchers in a rule has been retained from the existing code but has been adjusted to assert when it is used. Previously it would silently drop all but the first instruction matcher. The tablegen-erated file is not functionally changed but has more parentheses and no longer attempts to format the if-statements since keeping track of the indentation is tricky in the presence of the matcher hierarchy. It would be nice to have CMakes tablegen() run the output through clang-format (when available) so we don't have to complicate TableGen with pretty-printing. It's also worth mentioning that this hierarchy will also be able to emit TableGen definitions and test cases in the near future. This is the reason for favouring explicit emit*() calls rather than the << operator. Reviewers: aditya_nandakumar, rovka, t.p.northover, qcolombet, ab Reviewed By: ab Subscribers: igorb, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D28942 llvm-svn: 293172
* [globalisel] Fix an unused variable warning when NDEBUG is defined.Daniel Sanders2017-01-201-1/+1
| | | | llvm-svn: 292653
* Re-commit: [globalisel] Tablegen-erate current Register Bank InformationDaniel Sanders2017-01-194-1/+320
| | | | | | | | | | | | | | | | | | | | | Summary: Adds a RegisterBank tablegen class that can be used to declare the register banks and an associated tablegen pass to generate the necessary code. Changes since first commit attempt: * Added missing guards * Added more missing guards * Found and fixed a use-after-free bug involving Twine locals Reviewers: t.p.northover, ab, rovka, qcolombet Reviewed By: qcolombet Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka Differential Revision: https://reviews.llvm.org/D27338 llvm-svn: 292478
* Re-revert: [globalisel] Tablegen-erate current Register Bank InformationDaniel Sanders2017-01-184-317/+1
| | | | | | | More missing guards. My build didn't notice it due to a stale file left over from a Global ISel build. llvm-svn: 292369
* Re-commit: [globalisel] Tablegen-erate current Register Bank InformationDaniel Sanders2017-01-184-1/+317
| | | | | | | | | | | | | | | | | | | | | | | Summary: Adds a RegisterBank tablegen class that can be used to declare the register banks and an associated tablegen pass to generate the necessary code. Changes since last commit: The new tablegen pass is now correctly guarded by LLVM_BUILD_GLOBAL_ISEL and this should fix the buildbots however it may not be the whole fix. The previous buildbot failures suggest there may be a memory bug lurking that I'm unable to reproduce (including when using asan) or spot in the source. If they re-occur on this commit then I'll need assistance from the bot owners to track it down. Reviewers: t.p.northover, ab, rovka, qcolombet Reviewed By: qcolombet Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka Differential Revision: https://reviews.llvm.org/D27338 llvm-svn: 292367
* [X86] Fix for bugzilla 31576 - add support for "data32" instruction prefixMarina Yatsina2017-01-181-0/+4
| | | | | | | | | | | This patch fixes bugzilla 31576 (https://llvm.org/bugs/show_bug.cgi?id=31576). "data32" instruction prefix was not defined in the llvm. An exception had to be added to the X86 tablegen and AsmPrinter because both "data16" and "data32" are encoded to 0x66 (but in different modes). Differential Revision: https://reviews.llvm.org/D28468 llvm-svn: 292352
* Revert r292132: [globalisel] Tablegen-erate current Register Bank ↵Daniel Sanders2017-01-164-317/+1
| | | | | | | | | Information'... Several buildbots encountered a crash in tablegen when building this commit. Reverting while I investigate the cause. llvm-svn: 292136
* [globalisel] Tablegen-erate current Register Bank InformationDaniel Sanders2017-01-164-1/+317
| | | | | | | | | | | | | | Summary: Adds a RegisterBank tablegen class that can be used to declare the register banks and an associated tablegen pass to generate the necessary code. Reviewers: t.p.northover, ab, rovka, qcolombet Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka Differential Revision: https://reviews.llvm.org/D27338 llvm-svn: 292132
* [X86] Merge the disassemblers handling of the different TYPE_RELs by getting ↵Craig Topper2017-01-161-6/+6
| | | | | | the size information from the ENCODING field. NFCI llvm-svn: 292096
* [X86] Reduce the number of operand 'types' the disassembler needs to deal ↵Craig Topper2017-01-161-87/+86
| | | | | | | | | with. NFCI We were frequently checking for a list of types and the different types conveyed no real information. So lump them together explicitly. llvm-svn: 292095
* [AVX-512] Begin giving the disassembler a way to recognize that VSIB is a ↵Craig Topper2017-01-161-15/+17
| | | | | | | | different encoding than regular addressing modes. This part first teaches it not to check error if EVEX.V2 is used by a VSIB instruction. llvm-svn: 292093
* [AVX-512] Correct memory operand size for VPGATHERQPS and VPGATHERQDCraig Topper2017-01-161-0/+2
| | | | | | | | | with ZMM index. Similar for SCATTER and the prefetch gather and scatter instructions. Fixes PR31618. llvm-svn: 292088
* Mark comparator call operator as constEric Fiselier2016-12-271-1/+1
| | | | llvm-svn: 290636
* [GlobalISel] Add basic Selector-emitter tblgen backend.Ahmed Bougacha2016-12-215-1/+399
| | | | | | | | | | | | | | | | | This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
* [TableGen] Use 'unsigned' instead of 'bool' in a place where the code ↵Craig Topper2016-12-191-1/+1
| | | | | | conditionally assigns numeric values. They happen to be 0 and 1 so this is NFC. llvm-svn: 290088
* Implement LaneBitmask::any(), use it to replace !none(), NFCIKrzysztof Parzyszek2016-12-162-5/+5
| | | | llvm-svn: 289974
* Fix ubsan failures in lane mask shiftsKrzysztof Parzyszek2016-12-151-4/+8
| | | | llvm-svn: 289826
* Extract LaneBitmask into a separate typeKrzysztof Parzyszek2016-12-153-66/+73
| | | | | | | | | | | | Specifically avoid implicit conversions from/to integral types to avoid potential errors when changing the underlying type. For example, a typical initialization of a "full" mask was "LaneMask = ~0u", which would result in a value of 0x00000000FFFFFFFF if the type was extended to uint64_t. Differential Revision: https://reviews.llvm.org/D27454 llvm-svn: 289820
* [AMDGPU, PowerPC, TableGen] Fix some Clang-tidy modernize and Include What ↵Eugene Zelenko2016-12-121-10/+14
| | | | | | You Use warnings; other minor fixes (NFC). llvm-svn: 289475
* [AMDGPU, PowerPC, TableGen] Fix some Clang-tidy modernize and Include What ↵Eugene Zelenko2016-12-091-13/+14
| | | | | | You Use warnings; other minor fixes (NFC). llvm-svn: 289282
* Summary: Currently there is no way to disable deprecated warning from asm ↵Weiming Zhao2016-12-051-1/+3
| | | | | | | | | | | | | | | | | | | | like this clang -target arm deprecated-asm.s -c deprecated-asm.s:30:9: warning: use of SP or PC in the list is deprecated stmia r4!, {r12-r14} We have to have an option what can disable it. Patched by Yin Ma! Reviewers: joey, echristo, weimingz Subscribers: llvm-commits, aemerson Differential Revision: https://reviews.llvm.org/D27219 llvm-svn: 288734
* TableGen/AsmMatcherEmitter: Bring sorting check back under EXPENSIVE_CHECKSMatthias Braun2016-12-051-3/+13
| | | | | | | | | | | Bring the sorting check back that I removed in r288655 but put it under EXPENSIVE_CHECKS this time. Also document that this the check isn't purely about having a sorted list but also about operator < having the correct transitive behavior. Apply the same to the other check in the file. llvm-svn: 288693
* TableGen/AsmMatcherEmitter: Trust that stable_sort worksMatthias Braun2016-12-051-10/+0
| | | | | | | | | A debug build of AsmMatcherEmitter would use a quadratic algorithm to check whether std::stable_sort() actually sorted. Let's hope the authors of our C++ standard library did that testing for us. Removing the check gives a 3x speedup in the X86 case. llvm-svn: 288655
* TableGen: Use StringInit instead of std::string for DagInit arg namesMatthias Braun2016-12-054-30/+34
| | | | llvm-svn: 288644
* TableGen: Use StringInit instead of std::string for DagInit nameMatthias Braun2016-12-051-4/+4
| | | | llvm-svn: 288643
* TableGen: Use StringRef instead of const std::string& in return vals.Matthias Braun2016-12-0418-37/+40
| | | | | | | This will allow to switch to a different string storage in an upcoming commit. llvm-svn: 288612
* [tablegen] Delete duplicates from a vector without skipping elementsVedant Kumar2016-12-011-0/+1
| | | | | | | | | | | | | | Tablegen's -gen-instr-info pass has a bug in its emitEnums() routine. The function intends for values in a vector to be deduplicated, but it accidentally skips over elements after performing a deletion. I think there are smarter ways of doing this deduplication, but we can do that in a follow-up commit if there's interest. See the thread: [PATCH] TableGen InstrMapping Bug fix. Patch by Tyler Kenney! llvm-svn: 288408
* Fix some Clang-tidy and Include What You Use warnings; other minor fixes (NFC).Eugene Zelenko2016-11-307-132/+219
| | | | | | This preparation to remove SetVector.h dependency on SmallSet.h. llvm-svn: 288256
* Apply clang-tidy's 'performance-faster-string-find' check to LLVM.Benjamin Kramer2016-11-301-1/+1
| | | | | | No functionality change intended. llvm-svn: 288235
* TableGen: Allow signed immediates for instruction aliasesJacob Baungard Hansen2016-11-241-1/+1
| | | | | | | | | | | | Patch by Daniel Cederman. Reviewers: stoklund, arsenm Subscribers: arsenm, llvm-commits Differential Revision: https://reviews.llvm.org/D27046 llvm-svn: 287856
* Add IntrInaccessibleMemOnly property for intrinsicsAndrew Kaylor2016-11-223-7/+60
| | | | | | Differential Revision: https://reviews.llvm.org/D26485 llvm-svn: 287680
* [TableGen][ISel] When factoring ScopeMatcher, if the child of the ↵Craig Topper2016-11-221-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ScopeMatcher we're working on is also a ScopeMatcher, merge all its children into the one we're working on. There were several cases in X86 where we were unable to fully factor a ScopeMatcher but created nested ScopeMatchers for some portions of it. Then we created a SwitchType that split it up and further factored it so that we ended up with something like this: SwitchType Scope Scope Sequence of matchers Some other sequence of matchers EndScope Another sequence of matchers EndScope ...Next type This change turns it into this: SwitchType Scope Sequence of matchers Some other sequence of matchers Another sequence of matchers EndScope ...Next type Several other in-tree targets had similar nested scopes like this. Overall this doesn't save many bytes, but makes the isel output a little more regular. llvm-svn: 287624
* [Sparc] Use target name instead of namespace as prefix for MCRegisterClasses ↵Jacob Baungard Hansen2016-11-211-1/+1
| | | | | | | | | | | | | | | | | | | array Summary: For Sparc the namespace (SP) is different from the target name (Sparc), which causes the name of the array in this declaration to differ from the name used in the definition. Patch by Daniel Cederman. Reviewers: jyknight Subscribers: llvm-commits, jyknight Differential Revision: https://reviews.llvm.org/D23650 llvm-svn: 287528
* [TableGen][ISel] Do a better job of factoring ScopeMatchers created during ↵Craig Topper2016-11-211-3/+11
| | | | | | | | | | creation of SwitchTypeMatcher. Previously we were factoring when the ScopeMatcher was initially created, but it might get more Matchers added to it later. Delay factoring until we have fully created/populated the ScopeMatchers. This reduces X86 isel tables by 154 bytes. llvm-svn: 287520
* Try again to fix unused variable warning on lld-x86_64-darwin13 after r287439.Daniel Sanders2016-11-191-1/+6
| | | | | | | The previous attempt didn't work. I assume LLVM_ATTRIBUTE_UNUSED isn't available on that machine. llvm-svn: 287442
* Check that emitted instructions meet their predicates on all targets except ↵Daniel Sanders2016-11-196-30/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | ARM, Mips, and X86. Summary: * ARM is omitted from this patch because this check appears to expose bugs in this target. * Mips is omitted from this patch because this check either detects bugs or deliberate emission of instructions that don't satisfy their predicates. One deliberate use is the SYNC instruction where the version with an operand is correctly defined as requiring MIPS32 while the version without an operand is defined as an alias of 'SYNC 0' and requires MIPS2. * X86 is omitted from this patch because it doesn't use the tablegen-erated MCCodeEmitter infrastructure. Patches for ARM and Mips will follow. Depends on D25617 Reviewers: tstellarAMD, jmolloy Subscribers: wdng, jmolloy, aemerson, rengolin, arsenm, jyknight, nemanjai, nhaehnle, tstellarAMD, llvm-commits Differential Revision: https://reviews.llvm.org/D25618 llvm-svn: 287439
* [tablegen] Merge duplicate definitions of getMinimalTypeForRange. NFC.Daniel Sanders2016-11-196-37/+72
| | | | | | | | | | | | Summary: Depends on D25614 Reviewers: qcolombet Subscribers: qcolombet, beanz, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D25617 llvm-svn: 287438
* Fix -Wunused introduced in r286945 for release builds.Daniel Sanders2016-11-151-0/+2
| | | | llvm-svn: 286946
* [tablegen] Extract portions of AsmMatcherEmitter for re-use by another ↵Daniel Sanders2016-11-154-89/+158
| | | | | | | | | | | | | | | | | | | generator. NFC. Summary: This change is preparation for a change that will allow targets to verify that the instructions they emit meet the predicates they specify. This is useful to ensure that C++ legalization/lowering/instruction-selection doesn't incorrectly select code for a different subtarget than intended. Such cases are not caught by the integrated assembler when emitting instructions directly to an object file. Reviewers: qcolombet Subscribers: qcolombet, beanz, mgorny, llvm-commits, modocache Differential Revision: https://reviews.llvm.org/D25614 llvm-svn: 286945
* Re-apply r286384, "X86: Introduce the "relocImm" ComplexPattern, which ↵Peter Collingbourne2016-11-093-7/+13
| | | | | | | | | represents a relocatable immediate.", with a fix for 32-bit x86. Teach X86InstrInfo::analyzeCompare() not to crash on CMP and SUB instructions that take a global address operand. llvm-svn: 286420
* Revert r286384, "X86: Introduce the "relocImm" ComplexPattern, which ↵Peter Collingbourne2016-11-093-13/+7
| | | | | | | | | represents a relocatable immediate." Suspected to be the cause of a sanitizer-windows bot failure: Assertion failed: isImm() && "Wrong MachineOperand accessor", file C:\b\slave\sanitizer-windows\llvm\include\llvm/CodeGen/MachineOperand.h, line 420 llvm-svn: 286385
OpenPOWER on IntegriCloud