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* [X86] Split the VEX_WPrefix in X86Inst tablegen class into 3 separate fields ↵Craig Topper2019-04-091-6/+4
| | | | | | with clear meanings. llvm-svn: 357970
* [X86] Merge the different Jcc instructions for each condition code into ↵Craig Topper2019-04-051-0/+1
| | | | | | | | | | | | | | | | | | | | | single instructions that store the condition code as an operand. Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon Reviewed By: RKSimon Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60228 llvm-svn: 357802
* [X86] Merge the different SETcc instructions for each condition code into ↵Craig Topper2019-04-051-2/+2
| | | | | | | | | | | | | | | | | | | | | single instructions that store the condition code as an operand. Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between SETcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: andreadb, courbet, RKSimon, spatel, lebedev.ri Reviewed By: andreadb Subscribers: hiraditya, lebedev.ri, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60138 llvm-svn: 357801
* [X86] Merge the different CMOV instructions for each condition code into ↵Craig Topper2019-04-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | single instructions that store the condition code as an immediate. Summary: Reorder the condition code enum to match their encodings. Move it to MC layer so it can be used by the scheduler models. This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between CMOV instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. This does complicate the scheduler models a little since we can't assign the A and BE instructions to a separate class now. I plan to make similar changes for SETcc and Jcc. Reviewers: RKSimon, spatel, lebedev.ri, andreadb, courbet Reviewed By: RKSimon Subscribers: gchatelet, hiraditya, kristina, lebedev.ri, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60041 llvm-svn: 357800
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [X86] Add a new VEX_WPrefix encoding to tag EVEX instruction that have ↵Craig Topper2018-06-191-1/+1
| | | | | | | | | | | | | | VEX.W==1, but can be converted to their VEX equivalent that uses VEX.W==0. EVEX makes heavy use of the VEX.W bit to indicate 64-bit element vs 32-bit elements. Many of the VEX instructions were split into 2 versions with different masking granularity. The EVEX->VEX table generate can collapse the two versions if the VEX version uses is tagged as VEX_WIG. But if the VEX version is instead marked VEX.W==0 we can't combine them because we don't know if there is also a VEX version with VEX.W==1. This patch adds a new VEX_W1X tag that indicates the EVEX instruction encodes with VEX.W==1, but is safe to convert to a VEX instruction with VEX.W==0. This allows us to remove a bunch of manual EVEX->VEX table entries. We may want to look into splitting up the VEX_WPrefix field which would simplify the disassembler. llvm-svn: 335017
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-011-1/+1
| | | | | | | | | | | | | | | | We've been running doxygen with the autobrief option for a couple of years now. This makes the \brief markers into our comments redundant. Since they are a visual distraction and we don't want to encourage more \brief markers in new code either, this patch removes them all. Patch produced by for i in $(git grep -l '\\brief'); do perl -pi -e 's/\\brief //g' $i & done Differential Revision: https://reviews.llvm.org/D46290 llvm-svn: 331272
* [X86] Reduce number of OpPrefix bits in TSFlags to 2. NFCICraig Topper2018-04-031-1/+1
| | | | | | TSFlag doesn't need to disambiguate NoPrfx from PS. So shift the encodings so PS is NoPrfx|0x4. llvm-svn: 329049
* [X86] Merge the Has3DNow0F0FOpcode TSFlag into the OpMap encoding. NFCCraig Topper2018-03-241-3/+1
| | | | | | The 3DNow instructions are encoded a little weird, but we can still represent it as an opcode map. llvm-svn: 328410
* [X86][3DNOW] Teach decoder about AMD 3DNow! instrsRafael Auler2018-02-151-6/+8
| | | | | | | | | | | | | | | | | | | Summary: This patch makes the decoder understand old AMD 3DNow! instructions that have never been properly supported in the X86 disassembler, despite being supported in other subsystems. Hopefully this should make the X86 decoder more complete with respect to binaries containing legacy code. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: llvm-commits, maksfb, bruno Differential Revision: https://reviews.llvm.org/D43311 llvm-svn: 325295
* [X86] Fix disassembly of EVEX rounding control and SAE instructions.Craig Topper2017-10-231-0/+2
| | | | | | Fixes PR31955. llvm-svn: 316308
* fix trivial typos in comments; NFCHiroshi Inoue2017-07-041-1/+1
| | | | llvm-svn: 307075
* [X86] Moving X86Local namespace from .cpp to .h file to use it in memory ↵Ayman Musa2017-05-111-0/+122
| | | | | | | | folding TableGen backend. Differential Revision: https://reviews.llvm.org/D32797 llvm-svn: 302791
* [X86][AVX] Extend hasVEX_WPrefix bit to accept WIG value (W Ignore) + update ↵Ayman Musa2017-02-201-2/+2
| | | | | | | | | | | all AVX instructions with the new value. Add WIG value to all of AVX instructions which ignore the W-bit in their encoding, instead of giving them the default value of 0. This patch is needed for a follow up work on EVEX2VEX pass (replacing EVEX encoded instructions with their corresponding VEX version when possible). Differential Revision: https://reviews.llvm.org/D29876 llvm-svn: 295643
* [X86] Create a new instruction format to handle 4VOp3 encoding. This saves ↵Craig Topper2016-08-221-2/+0
| | | | | | one bit in TSFlags and simplifies MRMSrcMem/MRMSrcReg format handling. llvm-svn: 279424
* [X86] Create a new instruction format to handle MemOp4 encoding. This saves ↵Craig Topper2016-08-221-2/+0
| | | | | | one bit in TSFlags and simplifies MRMSrcMem/MRMSrcReg format handling. llvm-svn: 279423
* [NFC] Header cleanupMehdi Amini2016-04-181-1/+0
| | | | | | | | | | | | | | Removed some unused headers, replaced some headers with forward class declarations. Found using simple scripts like this one: clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap' Patch by Eugene Kosov <claprix@yandex.ru> Differential Revision: http://reviews.llvm.org/D19219 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266595
* [TableGen] Stop passing by reference an integer that doesn't get modified. NFCCraig Topper2016-02-161-1/+1
| | | | llvm-svn: 260934
* [TableGen] Remove unused member variable. NFCCraig Topper2016-02-161-2/+0
| | | | llvm-svn: 260933
* [X86] Remove the single AdSize indicator and replace it with separate ↵Craig Topper2014-12-241-2/+2
| | | | | | | | AdSize16/32/64 flags. This removes a hardcoded list of instructions in the CodeEmitter. Eventually I intend to remove the predicates on the affected instructions since in any given mode two of them are valid if we supported addr32/addr16 prefixes in the assembler. llvm-svn: 224809
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-2/+2
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* [X86] AVX512: Add disassembler support for compressed displacementAdam Nemet2014-07-171-0/+5
| | | | | | | | | | | | There are two parts here. First is to modify tablegen to adjust the encoding type ENCODING_RM with the scaling factor. The second is to use the new encoding types to compute the correct displacement in the decoder. Fixes <rdar://problem/17608489> llvm-svn: 213281
* [x86] Switch PAUSE instruction to use XS prefix instead of HasREPPrefix. ↵Craig Topper2014-02-201-2/+0
| | | | | | Remove HasREPPrefix support from disassembler table generator since its now only used by CodeGenOnly instructions. llvm-svn: 201767
* Remove unused method declaration.Craig Topper2014-02-131-3/+0
| | | | llvm-svn: 201301
* Remove filtering concept from X86 disassembler table generation. It's no ↵Craig Topper2014-02-131-19/+0
| | | | | | longer necessary. llvm-svn: 201299
* Remove special case filtering for instructions with lock prefix as they are ↵Craig Topper2014-02-121-2/+0
| | | | | | all marked with isCodeGenOnly already. llvm-svn: 201216
* TableGen/X86RecognizableInstr.h: Prune out-of-date "@param isSSE". ↵NAKAMURA Takumi2014-02-021-4/+0
| | | | | | [-Wdocumentation] llvm-svn: 200628
* Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 ↵Craig Topper2014-02-021-30/+25
| | | | | | meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
* Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field ↵Craig Topper2014-02-021-8/+6
| | | | | | in TSFlags. llvm-svn: 200624
* Separate x86 opcode maps and 0x66/0xf2/0xf3 prefixes from each other in the ↵Craig Topper2014-01-311-2/+4
| | | | | | TSFlags. This greatly simplifies the switch statements in the disassembler tables and the code emitters. llvm-svn: 200522
* Move REP out of the Prefix field of the X86 format. Give it its own bit. It ↵Craig Topper2014-01-311-0/+2
| | | | | | had special handling anyway and this enables a future patch. llvm-svn: 200520
* Simplify x86 disassembler table handling of when to use ↵Craig Topper2014-01-151-3/+3
| | | | | | TYPE_Rv/TYPE_R16/TYPE_R32 now that HasOpSizePrefix only means 16-bit instructions. llvm-svn: 199295
* The rest of r198588. Remove SegOvrBits from X86 TSFlags since they weren't ↵Craig Topper2014-01-061-2/+0
| | | | | | being used. llvm-svn: 198589
* Add a new x86 specific instruction flag to force some isCodeGenOnly ↵Craig Topper2014-01-051-1/+3
| | | | | | instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions. llvm-svn: 198543
* Remove unused HasFROperands field from disassembler.Craig Topper2014-01-021-3/+0
| | | | llvm-svn: 198332
* Remove unused function argument.Craig Topper2014-01-021-3/+1
| | | | llvm-svn: 198291
* AVX-512: added VPCONFLICT instruction and intrinsics,Elena Demikhovsky2013-11-031-0/+2
| | | | | | added EVEX_KZ to tablegen llvm-svn: 193959
* Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky2013-07-281-0/+10
| | | | | | | Added 512-bit operands printing. Added instruction formats for KNL instructions. llvm-svn: 187324
* Sort the #include lines for utils/...Chandler Carruth2012-12-041-5/+3
| | | | | | | I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
* Remove code for setting the VEX L-bit as a function of operand size from the ↵Craig Topper2012-09-191-4/+1
| | | | | | code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. llvm-svn: 164204
* Fix Doxygen issues:Dmitri Gribenko2012-09-131-8/+8
| | | | | | | | * wrap code blocks in \code ... \endcode; * refer to parameter names in paragraphs correctly (\arg is not what most people want -- it starts a new paragraph). llvm-svn: 163790
* Fix a bunch of -Wdocumentation warnings.Dmitri Gribenko2012-08-231-1/+1
| | | | llvm-svn: 162446
* Update GATHER instructions to support 2 read-write operands. Patch from ↵Craig Topper2012-07-121-1/+1
| | | | | | myself and Manman Ren. llvm-svn: 160110
* X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by ↵Craig Topper2012-02-271-0/+2
| | | | | | Kay Tiong Khoo. llvm-svn: 151510
* Add FMA4 instructions to disassembler.Craig Topper2011-12-301-1/+3
| | | | llvm-svn: 147367
* Add X86 BZHI instruction as well as BMI2 feature detection.Craig Topper2011-10-161-2/+2
| | | | llvm-svn: 142122
* Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand ↵Craig Topper2011-10-161-1/+3
| | | | | | 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen llvm-svn: 142105
* Add support in the disassembler for ignoring the L-bit on certain VEX ↵Craig Topper2011-10-041-0/+2
| | | | | | instructions. Mark instructions that have this behavior. Fixes PR10676. llvm-svn: 141065
* Move TableGen's parser and entry point into a libraryPeter Collingbourne2011-10-011-1/+1
| | | | | | This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
* Don't allow 32-bit only instructions to be disassembled in 64-bit mode. ↵Craig Topper2011-09-231-1/+3
| | | | | | Fixes part of PR10700. llvm-svn: 140370
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