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path: root/llvm/utils/TableGen/X86RecognizableInstr.cpp
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* Simplify x86 disassembler table handling of when to use ↵Craig Topper2014-01-151-22/+17
| | | | | | TYPE_Rv/TYPE_R16/TYPE_R32 now that HasOpSizePrefix only means 16-bit instructions. llvm-svn: 199295
* Remove stray comma in enum to satisfy -Wpedantic.Craig Topper2014-01-141-1/+1
| | | | llvm-svn: 199194
* Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix ↵Craig Topper2014-01-141-17/+36
| | | | | | | | and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode. This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke. llvm-svn: 199193
* [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understandDavid Woodhouse2014-01-081-0/+2
| | | | | | | | | | It seems there is no separate instruction class for having AdSize *and* OpSize bits set, which is required in order to disambiguate between all these instructions. So add that to the disassembler. Hm, perhaps we do need an AdSize16 bit after all? llvm-svn: 198759
* The rest of r198588. Remove SegOvrBits from X86 TSFlags since they weren't ↵Craig Topper2014-01-061-7/+0
| | | | | | being used. llvm-svn: 198589
* Use patterns to remove some duplicate instructions.Craig Topper2014-01-051-3/+1
| | | | llvm-svn: 198550
* Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack.Craig Topper2014-01-051-2/+1
| | | | llvm-svn: 198547
* Remove no longer needed x86 disassembler hack.Craig Topper2014-01-051-6/+0
| | | | llvm-svn: 198546
* Mark x86 _alt instructions as AsmParserOnly so they will be omitted from ↵Craig Topper2014-01-051-2/+1
| | | | | | disassembler without string matches. llvm-svn: 198545
* Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode ↵Craig Topper2014-01-051-3/+1
| | | | | | and remove disassmbler table emitter hack. llvm-svn: 198544
* Add a new x86 specific instruction flag to force some isCodeGenOnly ↵Craig Topper2014-01-051-1/+2
| | | | | | instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions. llvm-svn: 198543
* Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the ↵Craig Topper2014-01-051-3/+0
| | | | | | corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test. llvm-svn: 198530
* Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. ↵Craig Topper2014-01-041-2/+1
| | | | | | Remove disassembler hack. llvm-svn: 198515
* Remove JMP64pcrel32 (jmpq ). There are no tests for it. I'm pretty sure it ↵Craig Topper2014-01-041-2/+1
| | | | | | won't be emitted correctly since it was set to NoImm. And I can't prove that gas accepts 'jmpq' with an immediate either. Remove the special case for it from the disassembler table generator. llvm-svn: 198475
* Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr.Craig Topper2014-01-021-1/+0
| | | | llvm-svn: 198336
* Remove unused HasFROperands field from disassembler.Craig Topper2014-01-021-14/+0
| | | | llvm-svn: 198332
* Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack ↵Craig Topper2014-01-021-4/+0
| | | | | | from the disassembler table builder. llvm-svn: 198327
* Remove unnecessary stirng comparison from disassembler.Craig Topper2014-01-021-1/+0
| | | | llvm-svn: 198325
* Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler ↵Craig Topper2014-01-021-4/+0
| | | | | | table builder doesn't need to string match them to exclude them. llvm-svn: 198323
* Remove unused function argument.Craig Topper2014-01-021-2/+2
| | | | llvm-svn: 198291
* Remove modifierType/Base from X86 disassembler tables as they are no longer ↵Craig Topper2014-01-011-2/+0
| | | | | | used. Removes ~11.5K from static tables. llvm-svn: 198284
* Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are ↵Craig Topper2014-01-011-8/+4
| | | | | | really more like OrRegFrm so we don't need a difference since we can just mask bits. llvm-svn: 198278
* AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmpElena Demikhovsky2014-01-011-0/+2
| | | | | | | Printing rounding control. Enncoding for EVEX_RC (rounding control). llvm-svn: 198277
* Second attempt at Removing special form of AddRegFrm used by FP ↵Craig Topper2014-01-011-29/+25
| | | | | | instructions. These instructions can be handled by MRMXr instead. llvm-svn: 198276
* Revert r198238 and add FP disassembler tests. It didn't work and I didn't ↵Craig Topper2013-12-311-25/+29
| | | | | | realized we had no FP disassembler test cases. llvm-svn: 198265
* Remove special form of AddRegFrm used by FP instructions. These instructions ↵Craig Topper2013-12-301-29/+25
| | | | | | can be handled by MRMXr instead. llvm-svn: 198238
* Remove EscapeFilter. It's funcionality can be covered by correctly using ↵Craig Topper2013-12-301-2/+15
| | | | | | ExtendedFilter and ExactFilter. No functional change. llvm-svn: 198226
* [x86] Rename In32BitMode predicate to Not64BitModeEric Christopher2013-12-201-2/+3
| | | | | | | | | | | That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse llvm-svn: 197768
* AVX-512: Added legal type MVT::i1 and VK1 register for it.Elena Demikhovsky2013-12-161-0/+7
| | | | | | | | | Added scalar compare VCMPSS, VCMPSD. Implemented LowerSELECT for scalar FP operations. I replaced FSETCCss, FSETCCsd with one node type FSETCCs. Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1. llvm-svn: 197384
* AVX-512: added VPCONFLICT instruction and intrinsics,Elena Demikhovsky2013-11-031-2/+5
| | | | | | added EVEX_KZ to tablegen llvm-svn: 193959
* Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps ↵Craig Topper2013-10-141-0/+3
| | | | | | instructions to parse either GR32 or GR64 without resorting to duplicating instructions. llvm-svn: 192567
* Remove more filters from the disassembler. Mark some AVX512 instructions as ↵Craig Topper2013-10-121-5/+0
| | | | | | CodeGenOnly. llvm-svn: 192525
* Mark some more instructions as CodeGenOnly. Remove filters from the ↵Craig Topper2013-10-121-4/+0
| | | | | | disassembler. llvm-svn: 192522
* Remove another unnecessary filter from the disassembler.Craig Topper2013-10-111-3/+0
| | | | llvm-svn: 192425
* Fix so CRC32r64r8 isn't accidentally filtered from the disassembler tables.Craig Topper2013-10-101-1/+1
| | | | llvm-svn: 192339
* More x86 disassembler filtering cleanup.Craig Topper2013-10-091-4/+1
| | | | llvm-svn: 192279
* Remove some old filters from the x86 disassembler table builder.Craig Topper2013-10-091-6/+0
| | | | llvm-svn: 192275
* Remove unneeded MMX instruction definition by moving pattern to an ↵Craig Topper2013-10-081-1/+0
| | | | | | equivalent instruction definition and removing the filtering from the disassembler table building. llvm-svn: 192175
* Remove some instructions that existed to provide aliases to the assembler. ↵Craig Topper2013-10-081-3/+1
| | | | | | Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. llvm-svn: 192171
* Remove some instructions that seem to only exist to trick the filtering ↵Craig Topper2013-10-071-1/+2
| | | | | | checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead. llvm-svn: 192090
* Add disassembler support for long encodings for INC/DEC in 32-bit mode.Craig Topper2013-10-071-1/+2
| | | | llvm-svn: 192086
* Add XOP disassembler support. Fixes PR13933.Craig Topper2013-10-031-2/+65
| | | | llvm-svn: 191874
* AVX-512: Added masked SHIFT commands, more encoding testsElena Demikhovsky2013-08-221-17/+23
| | | | llvm-svn: 189005
* Remove use of sprintf added to X86 disassembler tablegen code. Send message ↵Craig Topper2013-07-281-4/+2
| | | | | | with instruction name to errs() instead and use a generic message for the llvm_unreachable. Consistent with other places in this file. llvm-svn: 187333
* fixed compilation issueElena Demikhovsky2013-07-281-0/+1
| | | | llvm-svn: 187325
* Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky2013-07-281-4/+156
| | | | | | | Added 512-bit operands printing. Added instruction formats for KNL instructions. llvm-svn: 187324
* Add support for encoding the HLE XACQUIRE and XRELEASE prefixes.Stefanus Du Toit2013-06-181-0/+6
| | | | | | | | For decoding, keep the current behavior of always decoding these as their REP versions. In the future, this could be improved to recognize the cases where these behave as XACQUIRE and XRELEASE and decode them as such. llvm-svn: 184207
* Add CLAC/STAC instruction encoding/decoding supportMichael Liao2013-04-111-17/+19
| | | | | | | As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. llvm-svn: 179266
* x86 -- add the XTEST instructionDave Zarzycki2013-03-251-8/+9
| | | | llvm-svn: 177888
* Fixes disassembler crashes on 2013 Haswell RTM instructions.Kevin Enderby2013-03-111-0/+11
| | | | | | rdar://13318048 llvm-svn: 176828
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