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| author | David Woodhouse <dwmw2@infradead.org> | 2014-01-08 12:58:24 +0000 |
|---|---|---|
| committer | David Woodhouse <dwmw2@infradead.org> | 2014-01-08 12:58:24 +0000 |
| commit | 32da3c8f3be5fd98f433342415662ca982da2e69 (patch) | |
| tree | 6122ddfba4d7f65afced53e1bf10402e70e69f34 /llvm/utils/TableGen/X86RecognizableInstr.cpp | |
| parent | 374243a2902087ef4b08387b5597195737f31bc4 (diff) | |
| download | bcm5719-llvm-32da3c8f3be5fd98f433342415662ca982da2e69.tar.gz bcm5719-llvm-32da3c8f3be5fd98f433342415662ca982da2e69.zip | |
[x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand
It seems there is no separate instruction class for having AdSize *and*
OpSize bits set, which is required in order to disambiguate between all
these instructions. So add that to the disassembler.
Hm, perhaps we do need an AdSize16 bit after all?
llvm-svn: 198759
Diffstat (limited to 'llvm/utils/TableGen/X86RecognizableInstr.cpp')
| -rw-r--r-- | llvm/utils/TableGen/X86RecognizableInstr.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp index 1df04224376..ab97a5f5433 100644 --- a/llvm/utils/TableGen/X86RecognizableInstr.cpp +++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp @@ -456,6 +456,8 @@ InstructionContext RecognizableInstr::insnContext() const { else if (HasOpSizePrefix && (Prefix == X86Local::XS || Prefix == X86Local::T8XS)) insnContext = IC_XS_OPSIZE; + else if (HasOpSizePrefix && HasAdSizePrefix) + insnContext = IC_OPSIZE_ADSIZE; else if (HasOpSizePrefix) insnContext = IC_OPSIZE; else if (HasAdSizePrefix) |
