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path: root/llvm/utils/TableGen/X86DisassemblerTables.h
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* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [X86] Add a new disassembler opcode map for 3DNow. Stop treating 3DNow as an ↵Craig Topper2018-03-241-1/+2
| | | | | | | | attribute. This reduces the size of llvm-mc by at least 150k since we no longer have to multiply the attribute across 7 tables. llvm-svn: 328416
* [X86] Use unique_ptr to simplify memory management. NFCCraig Topper2018-03-241-1/+1
| | | | llvm-svn: 328413
* [X86] Fix disassembler table generation to prevent instructions tagged with ↵Craig Topper2017-10-231-0/+2
| | | | | | 'PS' being inherited into PD/XS/XD attribute entries. llvm-svn: 316345
* [X86] Update a doxygen comment in the disassembler tablegen code. NFCCraig Topper2017-10-231-0/+1
| | | | llvm-svn: 316309
* [X86] Teach the disassembler that some instructions use VEX.W==0 without a ↵Craig Topper2017-10-221-0/+1
| | | | | | | | corresponding VEX.W==1 instruction and we shouldn't treat them as if VEX.W is ignored. Fixes PR11304. llvm-svn: 316285
* fix trivial typos in comments; NFCHiroshi Inoue2017-07-041-1/+1
| | | | llvm-svn: 307075
* [X86] Make the instructions that use AdSize16/32/64 co-exist together ↵Craig Topper2015-01-021-1/+3
| | | | | | | | | | without using mode predicates. This is necessary to allow the disassembler to be able to handle AdSize32 instructions in 64-bit mode when address size prefix is used. Eventually we should probably also support 'addr32' and 'addr16' in the assembler to override the address size on some of these instructions. But for now we'll just use special operand types that will lookup the current mode size to select the right instruction. llvm-svn: 225075
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-2/+2
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of ↵Craig Topper2014-02-191-8/+5
| | | | | | 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. llvm-svn: 201641
* Add XOP disassembler support. Fixes PR13933.Craig Topper2013-10-031-1/+4
| | | | llvm-svn: 191874
* Filter out repeated sections from the X86 disassembler modRMTable. Saves ↵Craig Topper2013-09-301-35/+20
| | | | | | about ~43K from a released build. Unfortunately the disassembler tables are still upwards of 800K. llvm-svn: 191652
* Sort the #include lines for utils/...Chandler Carruth2012-12-041-2/+0
| | | | | | | I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
* Remove trailing whitespaceCraig Topper2012-07-311-25/+25
| | | | llvm-svn: 161031
* Add support in the disassembler for ignoring the L-bit on certain VEX ↵Craig Topper2011-10-041-1/+3
| | | | | | instructions. Mark instructions that have this behavior. Fixes PR10676. llvm-svn: 141065
* Don't allow 32-bit only instructions to be disassembled in 64-bit mode. ↵Craig Topper2011-09-231-1/+3
| | | | | | Fixes part of PR10700. llvm-svn: 140370
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-151-1/+1
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* Add support for the VIA PadLock instructions.Joerg Sonnenberger2011-04-041-3/+6
| | | | llvm-svn: 128826
* Table-driven disassembler for the X86 architecture (16-, 32-, and 64-bit Sean Callanan2009-12-191-0/+291
incarnations), integrated into the MC framework. The disassembler is table-driven, using a custom TableGen backend to generate hierarchical tables optimized for fast decode. The disassembler consumes MemoryObjects and produces arrays of MCInsts, adhering to the abstract base class MCDisassembler (llvm/MC/MCDisassembler.h). The disassembler is documented in detail in - lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime) - utils/TableGen/DisassemblerEmitter.cpp (table emitter) You can test the disassembler by running llvm-mc -disassemble for i386 or x86_64 targets. Please let me know if you encounter any problems with it. llvm-svn: 91749
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