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* AVX-512: Added all AVX-512 forms of Vector Convert for Float/Double/Int/Long ↵Elena Demikhovsky2015-07-131-2/+24
| | | | | | | | | | | | types. In this patch I have only encoding. Intrinsics and DAG lowering will be in the next patch. I temporary removed the old intrinsics test (just to split this patch). Half types are not covered here. Differential Revision: http://reviews.llvm.org/D11134 llvm-svn: 242023
* AVX-512: Added VPTESTM and VPTESTNM instructions for SKXElena Demikhovsky2015-04-211-0/+7
| | | | llvm-svn: 235383
* Use SmallVector instead of std::vector for uniquing X86 disassembler operand ↵Craig Topper2015-04-091-1/+2
| | | | | | sets. The number of operands is a small fixed size. llvm-svn: 234465
* Simplify some printing code by combining new lines onto previous strings. ↵Craig Topper2015-04-091-9/+3
| | | | | | Don't work so hard not to print a comma on the last entry of an array. llvm-svn: 234464
* Don't convert enum to strings just to put them in the uniquing map. Use the ↵Craig Topper2015-04-091-15/+12
| | | | | | enum directly. Only convert to a string for printing. llvm-svn: 234463
* AVX-512: Added mask and rounding mode for scalar arithmeticsElena Demikhovsky2015-03-011-0/+12
| | | | | | Added more tests for scalar instructions to destinguish between AVX and AVX-512 forms. llvm-svn: 230891
* [X86] Disassembler support for move to/from %rax with a 32-bit memory offset ↵Craig Topper2015-01-031-2/+8
| | | | | | is REX.W and AdSize prefix are both present. llvm-svn: 225099
* [X86] Make the instructions that use AdSize16/32/64 co-exist together ↵Craig Topper2015-01-021-7/+11
| | | | | | | | | | without using mode predicates. This is necessary to allow the disassembler to be able to handle AdSize32 instructions in 64-bit mode when address size prefix is used. Eventually we should probably also support 'addr32' and 'addr16' in the assembler to override the address size on some of these instructions. But for now we'll just use special operand types that will lookup the current mode size to select the right instruction. llvm-svn: 225075
* [X86] Fix disassembly of absolute moves to work correctly in 16 and 32-bit ↵Craig Topper2014-12-311-14/+14
| | | | | | modes with all 4 combinations of OpSize and AdSize prefixes being present or not. llvm-svn: 225036
* [X86] Remove the single AdSize indicator and replace it with separate ↵Craig Topper2014-12-241-0/+3
| | | | | | | | AdSize16/32/64 flags. This removes a hardcoded list of instructions in the CodeEmitter. Eventually I intend to remove the predicates on the affected instructions since in any given mode two of them are valid if we supported addr32/addr16 prefixes in the assembler. llvm-svn: 224809
* [AVX512] Extended avx512_sqrt_packed (sqrt instructions) to VL subset.Robert Khasanov2014-10-281-0/+5
| | | | | | Refactored through AVX512_maskable llvm-svn: 220806
* [AVX512] Extended avx512_binop_rm for AVX512VL subsets.Robert Khasanov2014-10-091-0/+4
| | | | | | | Added avx512_binop_rm_vl multiclass for VL subset Added encoding tests llvm-svn: 219390
* [SKX] avx512_icmp_packed multiclass extensionRobert Khasanov2014-08-251-0/+6
| | | | | | | | | | | | | Extended avx512_icmp_packed multiclass by masking versions. Added avx512_icmp_packed_rmb multiclass for embedded broadcast versions. Added corresponding _vl multiclasses. Added encoding tests for CPCMP{EQ|GT}* instructions. Add more fields for X86VectorVTInfo. Added AVX512VLVectorVTInfo that include X86VectorVTInfo for 512/256/128-bit versions Differential Revision: http://reviews.llvm.org/D5024 llvm-svn: 216383
* [SKX] Enabling load/store instructions: encodingRobert Khasanov2014-08-041-0/+11
| | | | | | | | Instructions: VMOVAPD, VMOVAPS, VMOVDQA8, VMOVDQA16, VMOVDQA32,VMOVDQA64, VMOVDQU8, VMOVDQU16, VMOVDQU32,VMOVDQU64, VMOVUPD, VMOVUPS, Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com> llvm-svn: 214719
* AVX-512: Added rrk, rrkz, rmk, rmkz, rmbk, rmbkz versions of AVX512 FP ↵Elena Demikhovsky2014-03-061-0/+2
| | | | | | | | packed instructions, added encoding tests for them. By Robert Khazanov. llvm-svn: 203098
* Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of ↵Craig Topper2014-02-191-5/+3
| | | | | | 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. llvm-svn: 201641
* Remove filtering concept from X86 disassembler table generation. It's no ↵Craig Topper2014-02-131-5/+1
| | | | | | longer necessary. llvm-svn: 201299
* Remove unnecessary include.Craig Topper2014-02-091-1/+0
| | | | llvm-svn: 201041
* [x86] Fix disassembly of MOV16ao16 et al.David Woodhouse2014-01-201-4/+10
| | | | | | | | | | The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It also turns out to have been unnecessary. The disassembler handles the AdSize prefix for itself, and doesn't care about the difference between (e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and don't worry about it. llvm-svn: 199654
* AVX-512: Embedded Rounding Control - encoding and printingElena Demikhovsky2014-01-131-2/+3
| | | | | | Changed intrinsics for vrcp14/vrcp28 vrsqrt14/vrsqrt28 - aligned with GCC. llvm-svn: 199102
* [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understandDavid Woodhouse2014-01-081-1/+4
| | | | | | | | | | It seems there is no separate instruction class for having AdSize *and* OpSize bits set, which is required in order to disambiguate between all these instructions. So add that to the disassembler. Hm, perhaps we do need an AdSize16 bit after all? llvm-svn: 198759
* Remove modifierType/Base from X86 disassembler tables as they are no longer ↵Craig Topper2014-01-011-24/+0
| | | | | | used. Removes ~11.5K from static tables. llvm-svn: 198284
* AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmpElena Demikhovsky2014-01-011-43/+48
| | | | | | | Printing rounding control. Enncoding for EVEX_RC (rounding control). llvm-svn: 198277
* AVX-512: decoder for AVX-512, made by Alexey Bader.Elena Demikhovsky2013-12-251-4/+26
| | | | llvm-svn: 198013
* AVX-512: added VPCONFLICT instruction and intrinsics,Elena Demikhovsky2013-11-031-3/+32
| | | | | | added EVEX_KZ to tablegen llvm-svn: 193959
* Add XOP disassembler support. Fixes PR13933.Craig Topper2013-10-031-0/+3
| | | | llvm-svn: 191874
* Filter out repeated sections from the X86 disassembler modRMTable. Saves ↵Craig Topper2013-09-301-52/+47
| | | | | | about ~43K from a released build. Unfortunately the disassembler tables are still upwards of 800K. llvm-svn: 191652
* Various x86 disassembler fixes.Craig Topper2013-09-301-6/+18
| | | | | | | | | | | Add VEX_LIG to scalar FMA4 instructions. Use VEX_LIG in some of the inheriting checks in disassembler table generator. Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts. Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set. Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases. Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms. llvm-svn: 191649
* Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky2013-07-281-6/+95
| | | | | | | Added 512-bit operands printing. Added instruction formats for KNL instructions. llvm-svn: 187324
* Sort the #include lines for utils/...Chandler Carruth2012-12-041-3/+2
| | | | | | | I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
* Add a new compression type to ModRM table that detects when the memory modRM ↵Craig Topper2012-09-131-2/+15
| | | | | | byte represent 8 instructions and the reg modRM byte represents up to 64 instructions. Reduces modRM table from 43k entreis to 25k entries. Based on a patch from Manman Ren. llvm-svn: 163774
* Change unsigned to a uint16_t in static disassembler tables to reduce the ↵Craig Topper2012-09-111-0/+4
| | | | | | table size. llvm-svn: 163594
* Add more indirection to the disassembler tables to reduce amount of space ↵Craig Topper2012-08-011-29/+53
| | | | | | used to store the operand types and encodings. Store only the unique combinations in a separate table and store indices in the instruction table. Saves about 32K of static data. llvm-svn: 161101
* Use uint8_t to store the InstructionContext table. Saves 768 bytes of static ↵Craig Topper2012-07-311-1/+1
| | | | | | data. llvm-svn: 161034
* Tidy up. Move for loop index declarations into for statements. Use unsigned ↵Craig Topper2012-07-311-39/+26
| | | | | | instead of uint16_t for loop indices. Use unsigned instead of uint32_t for arguments to raw_ostream.indent. llvm-svn: 161033
* Tidy up function argument formatting.Craig Topper2012-07-311-35/+17
| | | | llvm-svn: 161032
* Remove trailing whitespaceCraig Topper2012-07-311-31/+31
| | | | llvm-svn: 161030
* Use uint8_t instead of enums to store values in X86 disassembler table. ↵Craig Topper2012-03-041-8/+8
| | | | | | Shaves 150k off the size of X86DisassemblerDecoder.o llvm-svn: 151995
* X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by ↵Craig Topper2012-02-271-0/+9
| | | | | | Kay Tiong Khoo. llvm-svn: 151510
* Remove dead code. Improve llvm_unreachable text. Simplify some control flow.Ahmed Charles2012-02-191-2/+0
| | | | llvm-svn: 150918
* Reuse the enum names from X86Desc in the X86Disassembler.Benjamin Kramer2012-02-111-1/+1
| | | | | | | This requires some gymnastics to make it available for C code. Remove the names from the disassembler tables, making them relocation free. llvm-svn: 150303
* More tweaks to get the size of the X86 disassembler tables down.Craig Topper2012-02-091-7/+28
| | | | llvm-svn: 150167
* Flatten some of the arrays in the X86 disassembler tables to reduce space ↵Craig Topper2012-02-091-38/+38
| | | | | | needed to store pointers on 64-bit hosts and reduce relocations needed at startup. Part of PR11953. llvm-svn: 150161
* Remove unreachable code. (replace with llvm_unreachable to help GCC where ↵David Blaikie2012-01-171-1/+0
| | | | | | necessary) llvm-svn: 148284
* More AVX2 instructions and their intrinsics.Craig Topper2011-11-061-1/+6
| | | | llvm-svn: 143895
* Fix disassembling of popcntw. Also remove some code that says it accounts ↵Craig Topper2011-10-111-0/+7
| | | | | | for 64BIT_REXW_XD not existing, but it does exist. llvm-svn: 141642
* Revert part of r141274. Only need to change encoding for xchg %eax, %eax in ↵Craig Topper2011-10-071-0/+1
| | | | | | 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. llvm-svn: 141353
* Add support in the disassembler for ignoring the L-bit on certain VEX ↵Craig Topper2011-10-041-15/+13
| | | | | | instructions. Mark instructions that have this behavior. Fixes PR10676. llvm-svn: 141065
* Fix typo in r140954.Craig Topper2011-10-021-1/+0
| | | | llvm-svn: 140962
* Fix disassembler handling of CRC32 which is an odd instruction that uses ↵Craig Topper2011-10-011-0/+9
| | | | | | 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. llvm-svn: 140954
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