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authorCraig Topper <craig.topper@gmail.com>2015-01-02 07:02:25 +0000
committerCraig Topper <craig.topper@gmail.com>2015-01-02 07:02:25 +0000
commit055845f5cbf7a9a84765b505450cff6a0dbeffa0 (patch)
tree318e56a2369394d48da5f0ac6653d929d1742801 /llvm/utils/TableGen/X86DisassemblerTables.cpp
parent24ac830d7c86daa72b93277dc82013a4f1e919c1 (diff)
downloadbcm5719-llvm-055845f5cbf7a9a84765b505450cff6a0dbeffa0.tar.gz
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[X86] Make the instructions that use AdSize16/32/64 co-exist together without using mode predicates.
This is necessary to allow the disassembler to be able to handle AdSize32 instructions in 64-bit mode when address size prefix is used. Eventually we should probably also support 'addr32' and 'addr16' in the assembler to override the address size on some of these instructions. But for now we'll just use special operand types that will lookup the current mode size to select the right instruction. llvm-svn: 225075
Diffstat (limited to 'llvm/utils/TableGen/X86DisassemblerTables.cpp')
-rw-r--r--llvm/utils/TableGen/X86DisassemblerTables.cpp18
1 files changed, 11 insertions, 7 deletions
diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp
index 5c3931ff4c2..138a34b4dc9 100644
--- a/llvm/utils/TableGen/X86DisassemblerTables.cpp
+++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp
@@ -75,13 +75,13 @@ static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
/// @return - True if child is a subset of parent, false otherwise.
static inline bool inheritsFrom(InstructionContext child,
InstructionContext parent,
- bool VEX_LIG = false) {
+ bool VEX_LIG = false, bool AdSize64 = false) {
if (child == parent)
return true;
switch (parent) {
case IC:
- return(inheritsFrom(child, IC_64BIT) ||
+ return(inheritsFrom(child, IC_64BIT, AdSize64) ||
inheritsFrom(child, IC_OPSIZE) ||
inheritsFrom(child, IC_ADSIZE) ||
inheritsFrom(child, IC_XD) ||
@@ -89,7 +89,7 @@ static inline bool inheritsFrom(InstructionContext child,
case IC_64BIT:
return(inheritsFrom(child, IC_64BIT_REXW) ||
inheritsFrom(child, IC_64BIT_OPSIZE) ||
- inheritsFrom(child, IC_64BIT_ADSIZE) ||
+ (!AdSize64 && inheritsFrom(child, IC_64BIT_ADSIZE)) ||
inheritsFrom(child, IC_64BIT_XD) ||
inheritsFrom(child, IC_64BIT_XS));
case IC_OPSIZE:
@@ -117,7 +117,7 @@ static inline bool inheritsFrom(InstructionContext child,
inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
case IC_64BIT_OPSIZE:
return inheritsFrom(child, IC_64BIT_REXW_OPSIZE) ||
- inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE);
+ (!AdSize64 && inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE));
case IC_64BIT_XD:
return(inheritsFrom(child, IC_64BIT_REXW_XD));
case IC_64BIT_XS:
@@ -865,15 +865,19 @@ void DisassemblerTables::setTableFields(OpcodeType type,
const ModRMFilter &filter,
InstrUID uid,
bool is32bit,
- bool ignoresVEX_L) {
+ bool ignoresVEX_L,
+ unsigned addressSize) {
ContextDecision &decision = *Tables[type];
for (unsigned index = 0; index < IC_max; ++index) {
- if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
+ if ((is32bit || addressSize == 16) &&
+ inheritsFrom((InstructionContext)index, IC_64BIT))
continue;
+ bool adSize64 = addressSize == 64;
if (inheritsFrom((InstructionContext)index,
- InstructionSpecifiers[uid].insnContext, ignoresVEX_L))
+ InstructionSpecifiers[uid].insnContext, ignoresVEX_L,
+ adSize64))
setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],
filter,
uid,
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