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authorCraig Topper <craig.topper@gmail.com>2014-12-24 06:05:22 +0000
committerCraig Topper <craig.topper@gmail.com>2014-12-24 06:05:22 +0000
commitb86338f7b237f43bb6a711bf2a69d016351e8ea1 (patch)
tree0d707db942d4af1f967974e9ef2651403472fb84 /llvm/utils/TableGen/X86DisassemblerTables.cpp
parent0fe246e0793ff978b33ed79479caac50fe2e1391 (diff)
downloadbcm5719-llvm-b86338f7b237f43bb6a711bf2a69d016351e8ea1.tar.gz
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[X86] Remove the single AdSize indicator and replace it with separate AdSize16/32/64 flags.
This removes a hardcoded list of instructions in the CodeEmitter. Eventually I intend to remove the predicates on the affected instructions since in any given mode two of them are valid if we supported addr32/addr16 prefixes in the assembler. llvm-svn: 224809
Diffstat (limited to 'llvm/utils/TableGen/X86DisassemblerTables.cpp')
-rw-r--r--llvm/utils/TableGen/X86DisassemblerTables.cpp3
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp
index d7e981c8fdf..86cd0c7b6cf 100644
--- a/llvm/utils/TableGen/X86DisassemblerTables.cpp
+++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp
@@ -822,6 +822,9 @@ void DisassemblerTables::setTableFields(ModRMDecision &decision,
InstructionSpecifier &previousInfo =
InstructionSpecifiers[decision.instructionIDs[index]];
+ // FIXME this doesn't actually work. The MCInsts the disassembler
+ // create don't encode re-encode correctly. They just manage to mostly
+ // print correctly.
// Instructions such as MOV8ao8 and MOV8ao8_16 differ only in the
// presence of the AdSize prefix. However, the disassembler doesn't
// care about that difference in the instruction definition; it
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