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path: root/llvm/utils/TableGen/RegisterInfoEmitter.cpp
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* Use RegUnits to compute overlapping registers.Jakob Stoklund Olesen2012-05-161-3/+2
| | | | | | | | | | | TableGen already computes register units as the basic unit of interference. We can use that to compute the set of overlapping registers. This means that we can easily compute overlap sets for one register at a time. There is no benefit to computing all registers at once. llvm-svn: 156960
* TableGen'erate mapping physical registers to encoding values.Jim Grosbach2012-05-151-4/+26
| | | | | | | | | | | Many targets always use the same bitwise encoding value for physical registers in all (or most) instructions. Add this mapping to the .td files and TableGen'erate the information and expose an accessor in MCRegisterInfo. patch by Tom Stellard. llvm-svn: 156829
* Remove TargetRegisterClass::SuperRegClasses.Jakob Stoklund Olesen2012-05-041-51/+0
| | | | | | | | This manually enumerated list of super-register classes has been superceeded by the automatically computed super-register class masks available through SuperRegClassIterator. llvm-svn: 156151
* Use a shared implementation of getMatchingSuperRegClass().Jakob Stoklund Olesen2012-05-031-34/+1
| | | | | | TargetRegisterClass now gives access to the necessary tables. llvm-svn: 156122
* Add TargetRegisterClass::getSuperRegIndices().Jakob Stoklund Olesen2012-05-031-4/+4
| | | | | | | | This is a pointer into one of the tables used by getMatchingSuperRegClass(). It makes it possible to use a shared implementation of that function. llvm-svn: 156121
* Emit SuperRegMasks as part of the existing SubClassMask arrays.Jakob Stoklund Olesen2012-05-031-102/+83
| | | | | | | | | The RC->getSubClassMask() pointer now points to a sequence of register class bit masks. The first bit mask is the normal sub-class mask. The following masks are super-reg class masks used by getMatchingSuperRegClass(). llvm-svn: 156120
* Compress tables for getMatchingSuperRegClass().Jakob Stoklund Olesen2012-05-031-19/+67
| | | | | | | | Many register classes only have a few super-registers, so it is not necessary to keep individual bit masks for all possible sub-register indices. llvm-svn: 156083
* Don't override subreg functions in targets without subregisters.Jakob Stoklund Olesen2012-05-031-42/+39
| | | | | | | | Some targets have no sub-registers at all. Use the TargetRegisterInfo versions of composeSubRegIndices(), getSubClassWithSubReg(), and getMatchingSuperRegClass() for those targets. llvm-svn: 156075
* Remove 'XXXRegisterClass' from tablegen output. Targets should use ↵Craig Topper2012-04-211-3/+0
| | | | | | '&XXXRegClass' instead. llvm-svn: 155270
* TableGen'd RegPressure: Added getPressureSetName.Andrew Trick2012-04-201-1/+13
| | | | llvm-svn: 155234
* tblgen: remove duplicated newlines.Benjamin Kramer2012-04-181-1/+1
| | | | llvm-svn: 155038
* Move a few more warnings to use PrintWarning().Jim Grosbach2012-04-181-2/+4
| | | | llvm-svn: 155027
* Formatting.Jim Grosbach2012-04-181-3/+2
| | | | llvm-svn: 155025
* Tidy up. Add a '.' at the end of the sentence.Jim Grosbach2012-04-181-1/+1
| | | | llvm-svn: 155024
* TableGen's regpressure: emit per-registerclass weight limits.Andrew Trick2012-04-111-14/+14
| | | | llvm-svn: 154518
* Tablegen'd regpressure: emit the weighted pressure limit.Andrew Trick2012-04-111-1/+7
| | | | llvm-svn: 154477
* Added register unit sets to the target description.Andrew Trick2012-04-101-0/+76
| | | | | | | | | | This is a new algorithm that finds sets of register units that can be used to model registers pressure. This handles arbitrary, overlapping register classes. Each register class is associated with a (small) list of pressure sets. These are the dimensions of pressure affected by the register class's liveness. llvm-svn: 154374
* Tidy up spacing in some tablegen outputs.Craig Topper2012-04-031-9/+7
| | | | llvm-svn: 153937
* Emit the LLVM<->DWARF register mapping as a sorted table and use binary ↵Benjamin Kramer2012-04-011-43/+143
| | | | | | | | | | | | | | | search to do the lookup. This also avoids emitting the information twice, which led to code bloat. On i386-linux-Release+Asserts with all targets built this change shaves a whopping 1.3 MB off clang. The number is probably exaggerated by recent inliner changes but the methods were already enormous with the old inline cost computation. The DWARF reg -> LLVM reg mapping doesn't seem to have holes in it, so it could be a simple lookup table. I didn't implement that optimization yet to avoid potentially changing functionality. There is still some duplication both in tablegen and the generated code that should be cleaned up eventually. llvm-svn: 153837
* Reapply 153764 and 153761 with a fix.Jakob Stoklund Olesen2012-03-301-101/+76
| | | | | | | | | Use an explicit comparator instead of the default. The sets are sorted, but not using the default comparator. Hopefully, this will unbreak the Linux builders. llvm-svn: 153772
* Revert 153764 and 153761. They broke a --enable-optimized --enable-assertionsRafael Espindola2012-03-301-75/+101
| | | | | | --enable-expensive-checks build. llvm-svn: 153771
* Compress SimpleValueType lists by sharing.Jakob Stoklund Olesen2012-03-301-20/+13
| | | | | | Many register classes have the same value types. Share the table space. llvm-svn: 153764
* Compress register lists by sharing suffixes.Jakob Stoklund Olesen2012-03-301-81/+62
| | | | | | | | TableGen emits lists of sub-registers, super-registers, and overlaps. Put them all in a single table and use a SequenceToOffsetTable to share suffixes. llvm-svn: 153761
* Add more constness to CodeGenRegisters.Jakob Stoklund Olesen2012-03-291-2/+2
| | | | llvm-svn: 153667
* Add asserts to ensure that values will fit into the tables.Craig Topper2012-03-061-1/+16
| | | | llvm-svn: 152104
* Shrink and reorder fields in MCRegisterClass to reduce size of static data.Craig Topper2012-03-051-5/+5
| | | | llvm-svn: 152019
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper2012-03-051-7/+7
| | | | | | static data size. llvm-svn: 152016
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-2/+2
| | | | llvm-svn: 152001
* Use uint16_t instead of unsigned to store registers in reg classes. Reduces ↵Craig Topper2012-03-041-11/+11
| | | | | | static data size. llvm-svn: 151998
* Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper2012-03-041-2/+2
| | | | | | size of static data. llvm-svn: 151996
* Move getSubRegIndex out of generated code into MCRegisterInfo, devirtualize it.Benjamin Kramer2012-03-011-11/+0
| | | | llvm-svn: 151821
* Move TargetRegisterInfo::getSubReg() to MCRegisterInfo.Jim Grosbach2012-03-011-51/+56
| | | | | | | | Allows us to de-virtualize the function and provides access to it in the instruction printer, which is useful for handling composite physical registers (e.g., ARM register lists). llvm-svn: 151815
* Revert "Emit the SubRegTable with the smallest possible integer type."Jim Grosbach2012-03-011-2/+2
| | | | | | | | | | This reverts commit 151760. We want to move getSubReg() from TargetRegisterInfo into MCRegisterInfo, but to do that, the type of the lookup table needs to be the same for all targets. llvm-svn: 151814
* Make TargetRegisterClasses non-virtual by making the only virtual function a ↵Benjamin Kramer2012-03-011-44/+41
| | | | | | | | | | | function pointer. This allows us to make TRC non-polymorphic and value-initializable, eliminating a huge static initializer and a ton of cruft from the generated code. Shrinks ARMBaseRegisterInfo.o by ~100k. llvm-svn: 151806
* Implement getSubRegIndex as a linear search on the SubRegTable instead of ↵Benjamin Kramer2012-02-291-14/+6
| | | | | | | | | using a big switch. - The search bounds are constant, in the worst case (ARM target) it will scan over 30 uint16_ts. - This method isn't very hot, I had problems finding a testcase where it's called more than a dozen of times (no perf impact). llvm-svn: 151773
* Emit the SubRegTable with the smallest possible integer type.Benjamin Kramer2012-02-291-2/+2
| | | | | | Doesn't help ARM with its massive register set, but halves the size on x86 and all other targets. llvm-svn: 151760
* Tidy up. Spelling.Jim Grosbach2012-02-291-2/+2
| | | | llvm-svn: 151758
* Move the subregister indicies enum into the REGINFO_ENUM section.Jim Grosbach2012-02-291-15/+14
| | | | llvm-svn: 151756
* Switch TargetRegisterInfo::getSubReg() to use a lookup table.Jim Grosbach2012-02-291-18/+34
| | | | | | | | Instead of nested switch statements, use a lookup table. On ARM, this replaces a 23k (x86_64 release build) function with a 16k table. Its not unlikely to be faster, as well. llvm-svn: 151751
* Remove 'if' from getSuperRegisters, getSubRegisters, and getOverlaps that ↵Craig Topper2012-02-231-1/+1
| | | | | | were added in r151038. llvm-svn: 151246
* Declare register classes as const. Fix a couple pointers to register classes ↵Craig Topper2012-02-221-3/+4
| | | | | | that weren't already const. llvm-svn: 151138
* Make all pointers to TargetRegisterClass const since they are all pointers ↵Craig Topper2012-02-221-2/+2
| | | | | | to static data that should not be modified. llvm-svn: 151134
* Reorder some members in MCRegisterClass to remove padding on 64-bit builds.Craig Topper2012-02-211-2/+2
| | | | llvm-svn: 151043
* In generated RegisterInfo files, replace a pointer to the end of an array ↵Craig Topper2012-02-211-4/+2
| | | | | | with just the size of the array to avoid relocations. llvm-svn: 151041
* Merge some tables in generated RegisterInfo file. Store indices into larger ↵Craig Topper2012-02-211-28/+48
| | | | | | table instead of pointers to reduce relocations and shrink table size on 64-bit builds. Shaves ~24K off X86MCTargetDesc.o. Accidentally commited only part of this in r151038. llvm-svn: 151039
* Store just the SimpleValueType in the generated VT tables for each register ↵Benjamin Kramer2012-02-091-1/+1
| | | | | | class, eliminating static ctors. llvm-svn: 150173
* Don't map registers to the invalid dwarf register (-1). It's the default value.Benjamin Kramer2012-02-081-0/+3
| | | | | | | X86GenRegisterInfo.inc | 1032 ------------------------------------------------- 1 file changed, 1032 deletions(-) llvm-svn: 150080
* Value initialize MCRegisterClasses. Not sure how could miss this during the ↵Benjamin Kramer2012-02-081-2/+2
| | | | | | MCTargetDesc refactor. llvm-svn: 150076
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-051-4/+2
| | | | llvm-svn: 149814
* Avoid emitting empty arrays, they're not standard C++.Jakob Stoklund Olesen2012-02-011-6/+11
| | | | | | | It's only by luck that we haven't produced any yet, and clang refuses to compile them. llvm-svn: 149546
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