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path: root/llvm/utils/TableGen/InstrInfoEmitter.h
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* Write llvm-tblgen backends as functions instead of sub-classes.Jakob Stoklund Olesen2012-06-111-62/+0
| | | | | | | | | The TableGenBackend base class doesn't do much, and will be removed completely soon. Patch by Sean Silva! llvm-svn: 158311
* Remove incorrect comment.Jim Grosbach2012-04-111-1/+1
| | | | llvm-svn: 154533
* Tidy up. Whitespace.Jim Grosbach2012-04-111-4/+4
| | | | llvm-svn: 154531
* Move TableGen's parser and entry point into a libraryPeter Collingbourne2011-10-011-1/+1
| | | | | | This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-281-2/+3
| | | | llvm-svn: 134024
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-4/+0
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Remove RCBarriers from TargetInstrDesc.Evan Cheng2011-06-271-1/+0
| | | | llvm-svn: 133964
* Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.Jakob Stoklund Olesen2010-04-051-2/+0
| | | | | | | | | | | | | | | | | | | When a target instruction wants to set target-specific flags, it should simply set bits in the TSFlags bit vector defined in the Instruction TableGen class. This works well because TableGen resolves member references late: class I : Instruction { AddrMode AM = AddrModeNone; let TSFlags{3-0} = AM.Value; } let AM = AddrMode4 in def ADD : I; TSFlags gets the expected bits from AddrMode4 in this example. llvm-svn: 100384
* Replace std::iostreams with raw_ostream in TableGen.Daniel Dunbar2009-07-031-4/+4
| | | | | | | | - Sorry, I can't help myself. - No intended functionality change. llvm-svn: 74742
* Add RCBarriers to TargetInstrDesc. It's a list of register classes the given ↵Evan Cheng2008-10-171-0/+5
| | | | | | | | instruction can "clobber". For example, on x86 the call instruction can modify all of the XMM and fp stack registers. TableGen has been taught to generate the lists from instruction definitions. llvm-svn: 57722
* Move instruction flag inference out of InstrInfoEmitter and intoDan Gohman2008-04-031-5/+1
| | | | | | | | | | | | CodeGenDAGPatterns, where it can be used in other tablegen backends. This allows the inference to be done for DAGISelEmitter so that it gets accurate mayLoad/mayStore/isSimpleLoad flags. This brings MemOperand functionality back to where it was before 48329. However, it doesn't solve the problem of anonymous patterns which expand to code that does loads or stores. llvm-svn: 49123
* start inferring 'no side effects'.Chris Lattner2008-01-101-1/+1
| | | | llvm-svn: 45822
* remove some old hacky code that tried to infer whether a store Chris Lattner2008-01-061-1/+1
| | | | | | | | | | | occured in a pattern, but failed miserably. The new code works for any instruction that has a store in its pattern, including all the x86 mem op mem instructions. The only target-independent code that uses this is branch folding, so this won't change anything in practice. llvm-svn: 45648
* rearrange some code to allow inferring instr info from the pattern of the ↵Chris Lattner2008-01-061-0/+4
| | | | | | instr, but don't do so yet. llvm-svn: 45647
* final cleanups.Chris Lattner2008-01-061-5/+4
| | | | llvm-svn: 45644
* further simplifications and cleanupChris Lattner2008-01-061-2/+8
| | | | llvm-svn: 45643
* simplify some codeChris Lattner2008-01-061-3/+4
| | | | llvm-svn: 45642
* split enum emission out from InstrInfoEmitter into it's own tblgen backend.Chris Lattner2008-01-061-2/+0
| | | | llvm-svn: 45640
* remove attributions from utils.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45419
* simplify the way operand flags and constraints are handled, making it easierChris Lattner2006-11-061-1/+2
| | | | | | to extend. llvm-svn: 31481
* Unbreak VC++ build.Jeff Cohen2006-11-051-1/+1
| | | | llvm-svn: 31464
* Add operand constraints to TargetInstrInfo.Evan Cheng2006-11-011-1/+1
| | | | llvm-svn: 31333
* Emit itinerary class in instruction info.Jim Laskey2005-10-311-1/+6
| | | | llvm-svn: 24122
* Switch more code over to using getValueAsListOfDefs. Look at all the -'s. :)Chris Lattner2005-10-281-1/+1
| | | | llvm-svn: 24074
* Emit real operand info for instructions. This currently works but is badChris Lattner2005-08-191-0/+1
| | | | | | | in one way: the generated tables require dynamic initialization for the register classes. This will be fixed in a future patch. llvm-svn: 22919
* When emitting implicit use/def lists, only emit each unique list once. ThoughChris Lattner2005-08-181-2/+6
| | | | | | | | | | | | LLVM is able to merge identical static const globals, GCC isn't, and this caused some bloat in the generated data. This has a marginal effect on PPC, shrinking the implicit sets from 10->4, but shrinks X86 from 179 to 23, a much bigger reduction. This should speed up the register allocator as well by reducing the dcache footprint for this static data. llvm-svn: 22879
* Remove trailing whitespaceMisha Brukman2005-04-221-3/+3
| | | | llvm-svn: 21428
* Convert 'struct' to 'class' in various places to adhere to the coding standardsChris Lattner2004-10-271-1/+1
| | | | | | and work better with VC++. Patch contributed by Morten Ofstad! llvm-svn: 17281
* Add, and start using, the CodeGenInstruction class. This class representsChris Lattner2004-08-011-1/+3
| | | | | | an instance of the Instruction tablegen class. llvm-svn: 15385
* Put all LLVM code into the llvm namespace, as per bug 109.Brian Gaeke2003-11-111-0/+5
| | | | llvm-svn: 9903
* Added LLVM copyright header.John Criswell2003-10-201-0/+7
| | | | llvm-svn: 9305
* Move support/tools/* back into utilsChris Lattner2003-10-051-0/+34
llvm-svn: 8875
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