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path: root/llvm/utils/TableGen/CodeGenRegisters.cpp
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* Remove some unnecessary vector::reserve/assign calls.David Blaikie2014-11-291-9/+5
| | | | llvm-svn: 222959
* Remove indirection of vector<T*> in favor of deque<T>David Blaikie2014-11-291-36/+32
| | | | llvm-svn: 222958
* Use deque<T> rather than vector<T*> since it provides the same invalidation ↵David Blaikie2014-11-291-27/+19
| | | | | | | | | | | | | | | semantics (at least when removal is not needed) without the extra indirection/ownership complexity Order matters for this container, it seems (using a forward_list and replacing the original push_backs with emplace_fronts caused test failures). I didn't look too deeply into why. (& in retrospect, I might go back & change some of the forward_lists I introduced to deques anyway - since most don't require removal, deque is a more memory-friendly data structure (moderate locality while not invalidating pointers)) llvm-svn: 222950
* Constify some things in preparation for CodeGenSubRegIndex to be stored by ↵David Blaikie2014-11-291-22/+21
| | | | | | value in their container, removing the indirection llvm-svn: 222949
* Fix a few memory leaks in CodeGenRegBank.Craig Topper2014-11-281-0/+6
| | | | llvm-svn: 222930
* Remove StringMap::GetOrCreateValue in favor of StringMap::insertDavid Blaikie2014-11-191-3/+6
| | | | | | | | | | | | | | Having two ways to do this doesn't seem terribly helpful and consistently using the insert version (which we already has) seems like it'll make the code easier to understand to anyone working with standard data structures. (I also updated many references to the Entry's key and value to use first() and second instead of getKey{Data,Length,} and get/setValue - for similar consistency) Also removes the GetOrCreateValue functions so there's less surface area to StringMap to fix/improve/change/accommodate move semantics, etc. llvm-svn: 222319
* Fix some cases were ArrayRefs were being passed by reference. Also remove ↵Craig Topper2014-08-271-1/+1
| | | | | | 'const' from some other ArrayRef uses since its implicitly const already. llvm-svn: 216524
* Use range based for loops to avoid needing to re-mention SmallPtrSet size.Craig Topper2014-08-241-3/+2
| | | | llvm-svn: 216351
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-2/+2
| | | | | | definition below all of the header #include lines, TableGen edition. llvm-svn: 206846
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-151-6/+6
| | | | | | instead of comparing to nullptr. llvm-svn: 206254
* tblgen: Twinify PrintFatalError.Benjamin Kramer2014-03-291-1/+1
| | | | | | No functionality change. llvm-svn: 205110
* [C++11] Add 'override' keywords to tablegen code.Craig Topper2014-03-051-1/+1
| | | | llvm-svn: 202937
* [C++11] Use std::tie to simplify compare operators.Benjamin Kramer2014-03-031-5/+2
| | | | | | No functionality change. llvm-svn: 202751
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-021-4/+4
| | | | | | Remove the old functions. llvm-svn: 202636
* Now that we have C++11, turn simple functors into lambdas and remove a ton ↵Benjamin Kramer2014-03-011-11/+4
| | | | | | | | of boilerplate. No intended functionality change. llvm-svn: 202588
* Replace tablegen uses of EVT with MVT. Add isOverloaded() to MVT to ↵Craig Topper2014-01-241-1/+1
| | | | | | facilitate. Remove TGValueTypes.cpp since its unused now (and may have been before). llvm-svn: 200036
* Provide basic type safety for array_pod_sort comparators.Benjamin Kramer2013-09-221-3/+4
| | | | | | | | This makes using array_pod_sort significantly safer. The implementation relies on function pointer casting but that should be safe as we're dealing with void* here. llvm-svn: 191175
* comment typo.Andrew Trick2013-07-311-1/+1
| | | | llvm-svn: 187531
* Fix register pressure tables on ARM.Andrew Trick2013-07-311-3/+31
| | | | | | The heuristic that merges register pressure sets was bogus for ARM's S/D regs. llvm-svn: 187479
* Add tracing to the tblgen register pressure table generator.Andrew Trick2013-07-311-7/+63
| | | | llvm-svn: 187478
* RegPressure: Order the "pressure sets" by number of regunits per set.Andrew Trick2013-07-251-1/+26
| | | | | | This lets heuristics easily pick the most important set to follow. llvm-svn: 187108
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector ↵Craig Topper2013-07-141-1/+1
| | | | | | size. llvm-svn: 186274
* Improve the compression of the tablegen DiffLists by introducing a new sortChad Rosier2013-06-271-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | algorithm when assigning EnumValues to the synthesized registers. The current algorithm, LessRecord, uses the StringRef compare_numeric function. This function compares strings, while handling embedded numbers. For example, the R600 backend registers are sorted as follows: T1 T1_W T1_X T1_XYZW T1_Y T1_Z T2 T2_W T2_X T2_XYZW T2_Y T2_Z In this example, the 'scaling factor' is dEnum/dN = 6 because T0, T1, T2 have an EnumValue offset of 6 from one another. However, in other parts of the register bank, the scaling factors are different: dEnum/dN = 5: KC0_128_W KC0_128_X KC0_128_XYZW KC0_128_Y KC0_128_Z KC0_129_W KC0_129_X KC0_129_XYZW KC0_129_Y KC0_129_Z The diff lists do not work correctly because different kinds of registers have different 'scaling factors'. This new algorithm, LessRecordRegister, tries to enforce a scaling factor of 1. For example, the registers are now sorted as follows: T1 T2 T3 ... T0_W T1_W T2_W ... T0_X T1_X T2_X ... KC0_128_W KC0_129_W KC0_130_W ... For the Mips and R600 I see a 19% and 6% reduction in size, respectively. I did see a few small regressions, but the differences were on the order of a few bytes (e.g., AArch64 was 16 bytes). I suspect there will be even greater wins for targets with larger register files. Patch reviewed by Jakob. rdar://14006013 llvm-svn: 185094
* Make SubRegIndex size mandatory, following r183020.Ahmed Bougacha2013-05-311-1/+14
| | | | | | | This also makes TableGen able to compute sizes/offsets of synthesized indices representing tuples. llvm-svn: 183061
* Add a way to define the bit range covered by a SubRegIndex.Ahmed Bougacha2013-05-311-3/+5
| | | | | | | | | | | | | NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change the instances of SubRegIndex that have a comps template arg to use the ComposedSubRegIndex class instead. In TableGen land, this adds Size and Offset attributes to SubRegIndex, and the ComposedSubRegIndex class, for which the Size and Offset are computed by TableGen. This also adds an accessor in MCRegisterInfo, and Size/Offsets for the X86 and ARM subreg indices. llvm-svn: 183020
* Remove the MCRegAliasIterator tables and compute the aliases dynamically.Chad Rosier2013-05-281-49/+0
| | | | | | | | | | | | | | | | | | | | The size reduction in the RegDiffLists are rather dramatic. Here are a few size differences for MCTargetDesc.o files (before and after) in bytes: R600 - 36160B - 11184B - 69% reduction ARM - 28480B - 8368B - 71% reduction Mips - 816B - 576B - 29% reduction One side effect of dynamically computing the aliases is that the iterator does not guarantee that the entries are ordered or that duplicates have been removed. The documentation implies this is a safe assumption and I found no clients that requires these attributes (i.e., strict ordering and uniqueness). My local LNT tester results showed no execution-time failures or significant compile-time regressions (i.e., beyond what I would consider noise) for -O0g, -O2 and -O3 runs on x86_64 and i386 configurations. rdar://12906217 llvm-svn: 182783
* Add TargetRegisterInfo::getCoveringLanes().Jakob Stoklund Olesen2013-05-161-5/+23
| | | | | | | | This lane mask provides information about which register lanes completely cover super-registers. See the block comment before getCoveringLanes(). llvm-svn: 182034
* [TableGen] Fix ICE on MSVC 2012 Release builds.Michael J. Spencer2013-02-261-1/+3
| | | | llvm-svn: 176125
* Clarify intent.Jakob Stoklund Olesen2013-01-311-0/+6
| | | | llvm-svn: 174068
* TableGen: Keep track of superclass reference ranges.Jordan Rose2013-01-101-2/+4
| | | | | | | | | | def foo : bar; ~~~ This allows us to produce more precise diagnostics about a certain superclass, and even provide fixits. llvm-svn: 172085
* RegisterPressure API. Add support for physical register units.Andrew Trick2012-12-051-0/+29
| | | | | | | | | | | | | At build-time register pressure was always computed in terms of register units. But the compile-time API was expressed in terms of register classes because it was intended for virtual registers (and physical register units weren't yet used anywhere in codegen). Now that the codegen uses physreg units consistently, prepare for tracking register pressure also in terms of live units, not live registers. llvm-svn: 169360
* Sort the #include lines for utils/...Chandler Carruth2012-12-041-2/+2
| | | | | | | I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
* Remove exception handling usage from tblgen.Joerg Sonnenberger2012-10-251-19/+21
| | | | | | | | | | | Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. llvm-svn: 166712
* Don't use stack unwinding to provide the location information forJoerg Sonnenberger2012-10-241-2/+2
| | | | | | SetTheory, but pass down the location explicitly. llvm-svn: 166629
* Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. ↵Sylvestre Ledru2012-09-271-1/+1
| | | | | | See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767 llvm-svn: 164768
* Fix a typo 'iff' => 'if'Sylvestre Ledru2012-09-271-1/+1
| | | | llvm-svn: 164767
* Compute a map from register names to registers, rather than scanning the ↵Owen Anderson2012-09-111-0/+6
| | | | | | list of registers every time we want to look up a register by name. llvm-svn: 163659
* Add TRI::getSubRegIndexLaneMask().Jakob Stoklund Olesen2012-09-111-2/+49
| | | | | | | | | | | | | | | | | Sub-register lane masks are bitmasks that can be used to determine if two sub-registers of a virtual register will overlap. For example, ARM's ssub0 and ssub1 sub-register indices don't overlap each other, but both overlap dsub0 and qsub0. The lane masks will be accurate on most targets, but on targets that use sub-register indexes in an irregular way, the masks may conservatively report that two sub-register indices overlap when the eventually allocated physregs don't. Irregular register banks also mean that the bits in a lane mask can't be mapped onto register units, but the concept is similar. llvm-svn: 163630
* Clean the sub-reg index composition maps at emission.Jakob Stoklund Olesen2012-09-111-15/+0
| | | | | | | Preserve the Composites map in the CodeGenSubRegIndex class so it can be used to determine which sub-register indices can actually be composed. llvm-svn: 163629
* Print out the location of expanded multiclass defs in TableGen errors.Jakob Stoklund Olesen2012-08-221-2/+2
| | | | | | | | | | | | | | | | | | | When reporting an error for a defm, we would previously only report the location of the outer defm, which is not always where the error is. Now we also print the location of the expanded multiclass defs: lib/Target/X86/X86InstrSSE.td:2902:12: error: foo defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>, ^ lib/Target/X86/X86InstrSSE.td:2801:11: note: instantiated from multiclass defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128, ^ lib/Target/X86/X86InstrSSE.td:194:5: note: instantiated from multiclass def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), ^ llvm-svn: 162409
* Add a CoveringSubRegIndices field to SubRegIndex records.Jakob Stoklund Olesen2012-08-151-9/+22
| | | | | | | This can be used to tell TableGen to use a specific SubRegIndex instead of synthesizing one when discovering all sub-registers. llvm-svn: 161982
* Make synthesized sub-register indexes available in the target namespace.Jakob Stoklund Olesen2012-08-151-15/+21
| | | | | | | | | | | TableGen sometimes synthesizes missing sub-register indexes. Emit these indexes as enumerators in the target namespace along with the user-defined ones. Also take this opportunity to stop creating new Record objects for synthetic indexes. llvm-svn: 161964
* Remove support for 'CompositeIndices' and sub-register cycles.Jakob Stoklund Olesen2012-07-261-52/+19
| | | | | | | | | | | | Now that the weird X86 sub_ss and sub_sd sub-register indexes are gone, there is no longer a need for the CompositeIndices construct in .td files. Sub-register index composition can be specified on the SubRegIndex itself using the ComposedOf field. Also enforce unique names for sub-registers in TableGen. The same sub-register cannot be available with multiple sub-register indexes. llvm-svn: 160842
* Fix typos found by http://github.com/lyda/misspell-checkBenjamin Kramer2012-06-021-3/+3
| | | | llvm-svn: 157885
* Emit register unit lists for each register.Jakob Stoklund Olesen2012-05-291-0/+5
| | | | | | | | | | | | | | | | Register units are already used internally in TableGen to compute register pressure sets and overlapping registers. This patch makes them available to the code generators. The register unit lists are differentially encoded so they can be reused for many related registers. This keeps the total size of the lists below 200 bytes for most targets. ARM has the largest table at 560 bytes. Add an MCRegUnitIterator for traversing the register unit lists. It provides an abstract interface so the representation can be changed in the future without changing all clients. llvm-svn: 157650
* Also compute TopoSigs in synthetic register classes.Jakob Stoklund Olesen2012-05-221-2/+7
| | | | | | | CodeGenRegisterClass has two constructors. Both need to compute the TopoSigs BitVector. llvm-svn: 157271
* Use RegUnits to compute overlapping registers.Jakob Stoklund Olesen2012-05-161-71/+49
| | | | | | | | | | | TableGen already computes register units as the basic unit of interference. We can use that to compute the set of overlapping registers. This means that we can easily compute overlap sets for one register at a time. There is no benefit to computing all registers at once. llvm-svn: 156960
* Create a struct representing register units in TableGen.Jakob Stoklund Olesen2012-05-151-18/+6
| | | | | | | | | | | | Besides the weight, we also want to store up to two root registers per unit. Most units will have a single root, the leaf register they represent. Units created for ad hoc aliasing get two roots: The two aliasing registers. The root registers can be used to compute the set of overlapping registers. llvm-svn: 156792
* Consider ad hoc aliasing when building RegUnits.Jakob Stoklund Olesen2012-05-141-12/+41
| | | | | | | | | | | | | | | | | | | | | | | Register units can be used to compute if two registers overlap: A overlaps B iff units(A) intersects units(B). With this change, the above holds true even on targets that use ad hoc aliasing (currently only ARM). This means that register units can be used to implement regsOverlap() more efficiently, and the register allocator can use the concept to model interference. When there is no ad hoc aliasing, the register units correspond to the maximal cliques in the register overlap graph. This is optimal, no other register unit assignment can have fewer units. With ad hoc aliasing, weird things are possible, and we don't try too hard to compute the maximal cliques. The current approach is always correct, and it works very well (probably optimally) as long as the ad hoc aliasing doesn't have cliques larger than pairs. It seems unlikely that any target would need more. llvm-svn: 156763
* Record the ad hoc aliasing graph in CodeGenRegister.Jakob Stoklund Olesen2012-05-141-5/+11
| | | | | | | | | | | | | The ad hoc aliasing specified in the 'Aliases' list in .td files is currently only used by computeOverlaps(). It will soon be needed to build accurate register units as well, so build the undirected graph in CodeGenRegister::buildObjectGraph() instead. Aliasing is a symmetric relationship with only one direction specified in the .td files. Make sure both directions are represented in getExplicitAliases(). llvm-svn: 156762
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