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| author | Andrew Trick <atrick@apple.com> | 2012-12-05 06:47:12 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-12-05 06:47:12 +0000 |
| commit | 510e606e197c05b88bb19bd5865d9877a1178f4d (patch) | |
| tree | 98324468b2d0fc3d01294e99136eb3ce09132438 /llvm/utils/TableGen/CodeGenRegisters.cpp | |
| parent | d52ab339cbcef7fba1866cdacf020d21f68d334d (diff) | |
| download | bcm5719-llvm-510e606e197c05b88bb19bd5865d9877a1178f4d.tar.gz bcm5719-llvm-510e606e197c05b88bb19bd5865d9877a1178f4d.zip | |
RegisterPressure API. Add support for physical register units.
At build-time register pressure was always computed in terms of
register units. But the compile-time API was expressed in terms of
register classes because it was intended for virtual registers (and
physical register units weren't yet used anywhere in codegen).
Now that the codegen uses physreg units consistently, prepare for
tracking register pressure also in terms of live units, not live
registers.
llvm-svn: 169360
Diffstat (limited to 'llvm/utils/TableGen/CodeGenRegisters.cpp')
| -rw-r--r-- | llvm/utils/TableGen/CodeGenRegisters.cpp | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/CodeGenRegisters.cpp index 0db11d48eae..20d439f8f71 100644 --- a/llvm/utils/TableGen/CodeGenRegisters.cpp +++ b/llvm/utils/TableGen/CodeGenRegisters.cpp @@ -1589,6 +1589,35 @@ void CodeGenRegBank::computeRegUnitSets() { } assert(!RegClassUnitSets[RCIdx].empty() && "missing unit set for regclass"); } + + // For each register unit, ensure that we have the list of UnitSets that + // contain the unit. Normally, this matches an existing list of UnitSets for a + // register class. If not, we create a new entry in RegClassUnitSets as a + // "fake" register class. + for (unsigned UnitIdx = 0, UnitEnd = NumNativeRegUnits; + UnitIdx < UnitEnd; ++UnitIdx) { + std::vector<unsigned> RUSets; + for (unsigned i = 0, e = RegUnitSets.size(); i != e; ++i) { + RegUnitSet &RUSet = RegUnitSets[i]; + if (std::find(RUSet.Units.begin(), RUSet.Units.end(), UnitIdx) + == RUSet.Units.end()) + continue; + RUSets.push_back(i); + } + unsigned RCUnitSetsIdx = 0; + for (unsigned e = RegClassUnitSets.size(); + RCUnitSetsIdx != e; ++RCUnitSetsIdx) { + if (RegClassUnitSets[RCUnitSetsIdx] == RUSets) { + break; + } + } + RegUnits[UnitIdx].RegClassUnitSetsIdx = RCUnitSetsIdx; + if (RCUnitSetsIdx == RegClassUnitSets.size()) { + // Create a new list of UnitSets as a "fake" register class. + RegClassUnitSets.resize(RCUnitSetsIdx + 1); + RegClassUnitSets[RCUnitSetsIdx].swap(RUSets); + } + } } void CodeGenRegBank::computeDerivedInfo() { |

