summaryrefslogtreecommitdiffstats
path: root/llvm/utils/TableGen/CodeGenInstruction.h
Commit message (Collapse)AuthorAgeFilesLines
* Remove neverHasSideEffects support from TableGen CodeGenInstruction. ↵Craig Topper2014-11-261-1/+0
| | | | | | Everyone should use hasSideEffects now. llvm-svn: 222809
* Add isInsertSubreg property.Quentin Colombet2014-08-201-0/+1
| | | | | | | | | | | | | This patch adds a new property: isInsertSubreg and the related target hooks: TargetIntrInfo::getInsertSubregInputs and TargetInstrInfo::getInsertSubregLikeInputs to specify that a target specific instruction is a (kind of) INSERT_SUBREG. The approach is similar to r215394. <rdar://problem/12702965> llvm-svn: 216139
* Add isExtractSubreg property.Quentin Colombet2014-08-201-0/+1
| | | | | | | | | | | | | This patch adds a new property: isExtractSubreg and the related target hooks: TargetIntrInfo::getExtractSubregInputs and TargetInstrInfo::getExtractSubregLikeInputs to specify that a target specific instruction is a (kind of) EXTRACT_SUBREG. The approach is similar to r215394. <rdar://problem/12702965> llvm-svn: 216130
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-2/+2
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* Add isRegSequence property.Quentin Colombet2014-08-111-0/+1
| | | | | | | | | | | This patch adds a new property: isRegSequence and the related target hooks: TargetIntrInfo::getRegSequenceInputs and TargetInstrInfo::getRegSequenceLikeInputs to specify that a target specific instruction is a (kind of) REG_SEQUENCE. <rdar://problem/12702965> llvm-svn: 215394
* TableGen: use correct MIOperand when printing aliasesTim Northover2014-05-151-0/+2
| | | | | | | | | | | | | | Previously, TableGen assumed that every aliased operand consumed precisely 1 MachineInstr slot (this was reasonable because until a couple of days ago, nothing more complicated was eligible for printing). This allows a couple more ARM64 aliases to print so we can remove the special code. On the X86 side, I've gone for explicit AT&T size specifiers as the default, so turned off a few of the aliases that would have just started printing. llvm-svn: 208880
* TableGen/ARM64: print aliases even if they have syntax variants.Tim Northover2014-05-151-1/+1
| | | | | | | To get at least one use of the change (and some actual tests) in with its commit, I've enabled the AArch64 & ARM64 NEON mov aliases. llvm-svn: 208867
* iterator_range accessor for CodeGenTarget instruction list.Jim Grosbach2014-04-181-1/+0
| | | | llvm-svn: 206551
* iterator based accessors for CodeGenInstruction operand list.Jim Grosbach2014-04-181-0/+7
| | | | llvm-svn: 206550
* Replace ValueTypes.h with MachineValueType.h if possible.Patrik Hagglund2014-03-151-1/+1
| | | | | | | | | Utilize the previous move of MVT to a separate header for all trivial cases (that don't need any further restructuring). Reviewed By: Tim Northover llvm-svn: 204003
* Shrink the size of CodeGenInstruction a little bit by using bitfields. 32 ↵Craig Topper2014-02-051-32/+32
| | | | | | bools seemed excessive. llvm-svn: 200829
* Add an instruction deprecation feature to TableGen.Joey Gouly2013-09-121-0/+3
| | | | | | | | | | | | | | | | | | | | | | The 'Deprecated' class allows you to specify a SubtargetFeature that the instruction is deprecated on. The 'ComplexDeprecationPredicate' class allows you to define a custom predicate that is called to check for deprecation. For example: ComplexDeprecationPredicate<"MCR"> would mean you would have to define the following function: bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) Which returns 'false' for not deprecated, and 'true' for deprecated and store the warning message in 'Info'. The MCTargetAsmParser constructor was chaned to take an extra argument of the MCInstrInfo class, so out-of-tree targets will need to be changed. llvm-svn: 190598
* Sort the #include lines for utils/...Chandler Carruth2012-12-041-2/+2
| | | | | | | I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
* Remove exception handling usage from tblgen.Joerg Sonnenberger2012-10-251-4/+3
| | | | | | | | | | | Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. llvm-svn: 166712
* Heed guessInstructionProperties, and stop warning on redundant flags.Jakob Stoklund Olesen2012-08-241-0/+8
| | | | | | | | | | | | Emit TableGen errors if guessInstructionProperties is 0 and instruction properties can't be inferred from patterns. Allow explicit instruction properties even when they can be inferred. This patch doesn't change the TableGen output. Redundant properties are not yet verified because the tree has errors. llvm-svn: 162516
* Tristate mayLoad, mayStore, and hasSideEffects.Jakob Stoklund Olesen2012-08-231-1/+5
| | | | | | | Keep track of the set/unset state of these bits along with their true/false values, but treat '?' as '0' for now. llvm-svn: 162461
* Print out the location of expanded multiclass defs in TableGen errors.Jakob Stoklund Olesen2012-08-221-1/+1
| | | | | | | | | | | | | | | | | | | When reporting an error for a defm, we would previously only report the location of the outer defm, which is not always where the error is. Now we also print the location of the expanded multiclass defs: lib/Target/X86/X86InstrSSE.td:2902:12: error: foo defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>, ^ lib/Target/X86/X86InstrSSE.td:2801:11: note: instantiated from multiclass defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128, ^ lib/Target/X86/X86InstrSSE.td:194:5: note: instantiated from multiclass def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), ^ llvm-svn: 162409
* Add an MCID::Select flag and TII hooks for optimizing selects.Jakob Stoklund Olesen2012-08-161-0/+1
| | | | | | | | | | | | Select instructions pick one of two virtual registers based on a condition, like x86 cmov. On targets like ARM that support predication, selects can sometimes be eliminated by predicating the instruction defining one of the operands. Teach PeepholeOptimizer to recognize select instructions, and ask the target to optimize them. llvm-svn: 162059
* Teach the AsmMatcherEmitter to allow InstAlias' where the suboperands of a ↵Owen Anderson2012-06-081-2/+2
| | | | | | complex operand are called out explicitly in the asm string. llvm-svn: 158183
* Restore hasPostISelHook tblgen flag.Andrew Trick2011-09-201-0/+1
| | | | | | | | | | No functionality change. The hook makes it explicit which patterns require "special" handling. i.e. it self-documents tblgen deficiencies. I plan to add verification in ExpandISelPseudos and Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's too fragile. llvm-svn: 140160
* ARM isel bug fix for adds/subs operands.Andrew Trick2011-09-201-1/+0
| | | | | | | | | | | Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the full gamut of CPSR defs/uses including instructins whose "optional" cc_out operand is not really optional. This allowed removal of the hasPostISelHook to simplify the .td files and make the implementation more robust. Fixes rdar://10137436: sqlite3 miscompile llvm-svn: 140134
* Follow up to r138791.Evan Cheng2011-08-301-0/+1
| | | | | | | | | | | | Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to call a target hook to adjust the instruction. For ARM, this is used to adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC instructions have implicit def of CPSR (required since it now uses CPSR physical register dependency rather than "glue"). If the carry flag is used, then the target hook will *fill in* the optional operand with CPSR. Otherwise, the hook will remove the CPSR implicit def from the MachineInstr. llvm-svn: 138810
* Unconstify InitsDavid Greene2011-07-291-4/+4
| | | | | | Remove const qualifiers from Init references, per Chris' request. llvm-svn: 136531
* [AVX] Constify InitsDavid Greene2011-07-291-4/+4
| | | | | | | Make references to Inits const everywhere. This is the final step before making them unique. llvm-svn: 136485
* Add a new field to MCOperandInfo that contains information about the type of ↵Benjamin Kramer2011-07-141-3/+8
| | | | | | | | | | the Operand. - The actual values are from the MCOI::OperandType enum. - Teach tblgen to read it from the instruction definition. - This is a better implementation of the hacks in edis. llvm-svn: 135197
* Revert r134921, 134917, 134908 and 134907. They're causing failuresEric Christopher2011-07-111-4/+4
| | | | | | in multiple buildbots. llvm-svn: 134936
* [AVX] Make Inits FoldableDavid Greene2011-07-111-4/+4
| | | | | | | | | | | | | | | | | | Manage Inits in a FoldingSet. This provides several benefits: - Memory for Inits is properly managed - Duplicate Inits are folded into Flyweights, saving memory - It enforces const-correctness, protecting against certain classes of bugs The above benefits allow Inits to be used in more contexts, which in turn provides more dynamism to TableGen. This enhanced capability will be used by the AVX code generator to a fold common patterns together. llvm-svn: 134907
* Add isCodeGenOnly value to the CodeGenInstruction class.Jim Grosbach2011-07-071-0/+1
| | | | | | | So users of a CGI don't have to look up the value directly from the original Record; just like the rest of the convenience values in the class. llvm-svn: 134576
* Don't require pseudo-instructions to carry encoding information.Jim Grosbach2011-07-061-0/+1
| | | | | | | | | | For now this is distinct from isCodeGenOnly, as code-gen-only instructions can (and often do) still have encoding information associated with them. Once we've migrated all of them over to true pseudo-instructions that are lowered to real instructions prior to the printer/emitter, we can remove isCodeGenOnly and just use isPseudo. llvm-svn: 134539
* change OperandsSignature to use SmallVector<char> instead of std::vector<string>Chris Lattner2011-04-171-0/+1
| | | | | | since the strings are always exactly one character, and there are usually only 2-3 operands. llvm-svn: 129678
* - Add "Bitcast" target instruction property for instructions which performEvan Cheng2011-03-151-0/+1
| | | | | | | nothing more than a bitcast. - Teach tablegen to automatically infer "Bitcast" property. llvm-svn: 127667
* Trailing whitespace.Jim Grosbach2011-03-141-46/+46
| | | | llvm-svn: 127592
* Improve the AsmMatcher's ability to handle suboperands.Bob Wilson2011-01-261-3/+11
| | | | | | | | | | | | | | | When an operand class is defined with MIOperandInfo set to a list of suboperands, the AsmMatcher has so far required that operand to also define a custom ParserMatchClass, and InstAlias patterns have not been able to set the individual suboperands separately. This patch removes both of those restrictions. If a "compound" operand does not override the default ParserMatchClass, then the AsmMatcher will now parse its suboperands separately. If an InstAlias operand has the same class as the corresponding compound operand, then it will be handled as before; but if that check fails, TableGen will now try to match up a sequence of InstAlias operands with the corresponding suboperands. llvm-svn: 124314
* Precompute InstAlias operand mapping to result instruction operand indices.Bob Wilson2011-01-201-5/+4
| | | | | | | There should be no functional change from this, but I think it's simpler this way. llvm-svn: 123931
* Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,Evan Cheng2010-11-171-0/+1
| | | | | | | | | | | | | | | | | | | | | and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 llvm-svn: 119548
* add (and document) the ability for alias results to haveChris Lattner2010-11-061-1/+5
| | | | | | | | fixed physical registers. Start moving fp comparison aliases to the .td file (which default to using %st1 if nothing is specified). llvm-svn: 118352
* generalize alias support to allow the result of an alias toChris Lattner2010-11-061-1/+17
| | | | | | | add fixed immediate values. Move the aad and aam aliases to use this, and document it. llvm-svn: 118350
* fix a bug where we had an implicit assumption that theChris Lattner2010-11-061-0/+5
| | | | | | | | result instruction operand numbering matched the result pattern. Fixing this allows us to move the xchg/test aliases to the .td file. llvm-svn: 118334
* Reimplement BuildResultOperands to be in terms of the result instruction'sChris Lattner2010-11-061-4/+0
| | | | | | | | | | | | | | | | | | operand list instead of the operand list redundantly declared on the alias or instruction. With this change, we finally remove the ins/outs list on the alias. Before: def : InstAlias<(outs GR16:$dst), (ins GR8 :$src), "movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8:$src)>; After: def : InstAlias<"movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8:$src)>; This also makes the alias mechanism more general and powerful, which will be exploited in subsequent patches. llvm-svn: 118329
* disolve a hack, having CodeGenInstAlias decode the alias in the .tdChris Lattner2010-11-061-1/+17
| | | | | | file instead of the asmmatcher. llvm-svn: 118324
* rewrite EmitConvertToMCInst to iterate over the MCInst operands,Chris Lattner2010-11-021-1/+12
| | | | | | | | filling them in one at a time. Previously this iterated over the asmoperands, which left the problem of "holes". The new approach simplifies things. llvm-svn: 118104
* Implement enough of the missing instalias support to getChris Lattner2010-11-011-0/+3
| | | | | | | | | | | | | | | | | | aliases installed and working. They now work when the matched pattern and the result instruction have exactly the same operand list. This is now enough for us to define proper aliases for movzx and movsx, implementing rdar://8017633 and PR7459. Note that we do not accept instructions like: movzx 0(%rsp), %rsi GAS accepts this instruction, but it doesn't make any sense because we don't know the size of the memory operand. It could be 8/16/32 bits. llvm-svn: 117901
* define a new CodeGenInstAlias. It has an asmstring and operand list for now,Chris Lattner2010-11-011-1/+18
| | | | | | todo: the result field. llvm-svn: 117894
* factor the operand list (and related fields/operations) out of Chris Lattner2010-11-011-67/+93
| | | | | | CodeGenInstruction into its own helper class. No functionality change. llvm-svn: 117893
* avoid needless throw/catch/rethrow, stringref'ize some simple stuff.Chris Lattner2010-11-011-2/+2
| | | | llvm-svn: 117892
* eliminate the old InstFormatName which is always "AsmString",Chris Lattner2010-11-011-1/+1
| | | | | | simplify CodeGenInstruction. No functionality change. llvm-svn: 117891
* move FlattenVariants out of AsmMatcherEmitter into a sharedChris Lattner2010-11-011-0/+7
| | | | | | | | CodeGenInstruction::FlattenAsmStringVariants method. Use it to simplify the code in AsmWriterInst, which now no longer needs to worry about variants. llvm-svn: 117886
* Allow targets to optionally specify custom binary encoder functions forJim Grosbach2010-10-121-3/+8
| | | | | | | | operand values. This is useful for operands which require additional trickery to encode into the instruction. For example, the ARM shifted immediate and shifted register operands. llvm-svn: 116353
* When figuring out which operands match which encoding fields in an instruction,Jim Grosbach2010-10-111-0/+5
| | | | | | | try to match them by name first. If there is no by-name match, fall back to assuming they are in order (this was the previous behavior). llvm-svn: 116211
* trailing whitespaceJim Grosbach2010-10-081-15/+15
| | | | llvm-svn: 116068
OpenPOWER on IntegriCloud