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path: root/llvm/utils/TableGen/AsmWriterEmitter.cpp
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* [MC] Add parameter `Address` to MCInstrPrinter::printInstructionFangrui Song2020-01-061-7/+8
| | | | | | | | Follow-up of D72172. Reviewed By: jhenderson, rnk Differential Revision: https://reviews.llvm.org/D72180
* [MC] Rewrite tablegen for printInstrAlias to comiple faster, NFCReid Kleckner2019-12-061-95/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this change, the *InstPrinter.cpp files of each target where some of the slowest objects to compile in all of LLVM. See this snippet produced by ClangBuildAnalyzer: https://reviews.llvm.org/P8171$96 Search for "InstPrinter", and see that it shows up in a few places. Tablegen was emitting a large switch containing a sequence of operand checks, each of which created many conditions and many BBs. Register allocation and jump threading both did not scale well with such a large repetitive sequence of basic blocks. So, this change essentially turns those control flow structures into data. The previous structure looked like: switch (Opc) { case TGT::ADD: // check alias 1 if (MI->getOperandCount() == N && // check num opnds MI->getOperand(0).isReg() && // check opnd 0 ... MI->getOperand(1).isImm() && // check opnd 1 AsmString = "foo"; break; } // check alias 2 if (...) ... return false; The new structure looks like: OpToPatterns: Sorted table of opcodes mapping to pattern indices. \-> Patterns: List of patterns. Previous table points to subrange of patterns to match. \-> Conds: The if conditions above encoded as a kind and 32-bit value. See MCInstPrinter.cpp for the details of how the new data structures are interpreted. Here are some before and after metrics. Time to compile AArch64InstPrinter.cpp: 0m29.062s vs. 0m2.203s size of the obj: 3.9M vs. 676K size of clang.exe: 97M vs. 96M I have not benchmarked disassembly performance, but typically disassemblers are bottlenecked on IO and string processing, not alias matching, so I'm not sure it's interesting enough to be worth doing. Reviewers: RKSimon, andreadb, xbolva00, craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D70650
* [tblgen] Add getOperatorAsDef() to RecordDaniel Sanders2019-10-081-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: While working with DagInit's, it's often the case that you expect the operator to be a reference to a def. This patch adds a wrapper for this common case to reduce the amount of boilerplate callers need to duplicate repeatedly. getOperatorAsDef() returns the record if the DagInit has an operator that is a DefInit. Otherwise, it prints a fatal error. There's only a few pre-existing examples in LLVM at the moment and I've left a few instances of the code this simplifies as they had more specific error messages than the generic one this produces. I'm going to be using this a fair bit in my subsequent patches. Reviewers: bogner, volkan, nhaehnle Reviewed By: nhaehnle Subscribers: nhaehnle, hiraditya, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, lenary, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68424 llvm-svn: 374101
* [llvm-objdump] Implement -Mreg-names-raw/-std options.Igor Kudrin2019-02-261-5/+14
| | | | | | | | | | | | | | The --disassembler-options, or -M, are used to customize the disassembler and affect its output. The two implemented options allow selecting register names on ARM: * With -Mreg-names-raw, the disassembler uses rNN for all registers. * With -Mreg-names-std it prints sp, lr and pc for r13, r14 and r15, which is the default behavior of llvm-objdump. Differential Revision: https://reviews.llvm.org/D57680 llvm-svn: 354870
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [TableGen:AsmWriter] Cope with consecutive tied operands.Simon Tatham2018-12-141-9/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When you define an instruction alias as a subclass of InstAlias, you specify all the MC operands for the instruction it expands to, except for operands that are tied to a previous one, which you leave out in the expectation that the Tablegen output code will fill them in automatically. But the code in Tablegen's AsmWriter backend that skips over a tied operand was doing it using 'if' instead of 'while', because it wasn't expecting to find two tied operands in sequence. So if an instruction updates a pair of registers in place, so that its MC representation has two input operands tied to the output ones (for example, Arm's UMLAL instruction), then any alias which wants to expand to a special case of that instruction is likely to fail to match, because the indices of subsequent operands will be off by one in the generated printAliasInstr function. This patch re-indents some existing code, so it's clearest when viewed as a diff with whitespace changes ignored. Reviewers: fhahn, rengolin, sdesmalen, atanasyan, asb, jholewinski, t.p.northover, kparzysz, craig.topper, stoklund Reviewed By: rengolin Subscribers: javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D53816 llvm-svn: 349141
* [TableGen] Prevent double flattening of InstAlias asm strings in the asm ↵Craig Topper2018-06-181-9/+11
| | | | | | | | | | | | matcher emitter. Unlike CodeGenInstruction, CodeGenInstAlias was flatting asm strings in its constructor. For instructions it was the users responsibility to flatten the string. AsmMatcherEmitter didn't know this and treated them the same. This caused double flattening of InstAliases. This is mostly harmless unless the desired assembly string contains curly braces. The second flattening wouldn't know to ignore these and would remove the curly braces. And for variant 1 it would remove the contents of them as well. To mitigate this, this patch makes removes the flattening from the CodeGenIntAlias constructor and modifies AsmWriterEmitter to account for the flattening not having been done. llvm-svn: 334919
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-2/+2
| | | | | | | | | | | | | | | | The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
* [AArch64][TableGen] Skip tied result operands for InstAliasSander de Smalen2017-11-201-2/+15
| | | | | | | | | | | | | | | | | | | | Summary: This patch fixes an issue so that the right alias is printed when the instruction has tied operands. It checks the number of operands in the resulting instruction as opposed to the alias, and then skips over tied operands that should not be printed in the alias. This allows to generate the preferred assembly syntax for the AArch64 'ins' instruction, which should always be displayed as 'mov' according to the ARM Architecture Reference Manual. Several unit tests have changed as a result, but only to reflect the preferred disassembly. Some other InstAlias patterns (movk/bic/orr) needed a slight adjustment to stop them becoming the default and breaking other unit tests. Please note that the patch is mostly the same as https://reviews.llvm.org/D29219 which was reverted because of an issue found when running TableGen with the Address Sanitizer. That issue has been addressed in this iteration of the patch. Reviewers: rengolin, stoklund, huntergr, SjoerdMeijer, rovka Reviewed By: rengolin, SjoerdMeijer Subscribers: fhahn, aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D40030 llvm-svn: 318650
* fix printing of alias instructions by removing redundant spacingPetar Jovanovic2017-11-131-1/+3
| | | | | | | | | | | | Some alias instructions are printed with an extra space after the tab character. Fix this by skipping that space when the tab character is printed so that the instructions are aligned with the rest of the code. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D35946 llvm-svn: 318059
* [TableGen] Use StringRef instead of std::string for CodeGenInstruction ↵Craig Topper2017-07-071-2/+2
| | | | | | namespace. NFC llvm-svn: 307362
* [TableGen] Adapt more places to getValueAsString now returning a StringRef ↵Craig Topper2017-05-311-20/+24
| | | | | | instead of a std::string. llvm-svn: 304347
* [TableGen] Make Record::getValueAsString and getValueAsListOfStrings return ↵Craig Topper2017-05-311-1/+1
| | | | | | | | | | | | StringRefs instead of std::string Internally both these methods just return the result of getValue on either a StringInit or a CodeInit object. In both cases this returns a StringRef pointing to a string allocated in the BumpPtrAllocator so its not going anywhere. So we can just pass that StringRef along. This is a fairly naive patch that targets just the build failures caused by this change. There's additional work that can be done to avoid creating std::string at call sites that still think getValueAsString returns a std::string. I'll try to clean those up in future patches. Differential Revision: https://reviews.llvm.org/D33710 llvm-svn: 304325
* Add a wrapper around copy_if in STLExtras; NFCSanjoy Das2017-02-211-4/+3
| | | | | | I will add one more use for this in a later change. llvm-svn: 295685
* [TableGen][AsmWriterEmitter] Use a deterministic order to sort InstrAliasesQuentin Colombet2017-02-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Inside an alias group, when ordering instruction aliases, we rely on the priority field to sort them. When the priority is not set or more generally when there is a tie between two aliases, we used to rely on the lexicographic order. However, this order can change for the anonymous records when more instruction, intrinsic, etc. are inserted. For instance, given two anonymous records r1 and r2 with respective name A_999 and A_1000, their lexicography order will be r2 then r1. Now, if an instruction is added before them, their name will become respectively A_1000 and A_1001, thus the lexicography order will be r1 then r2, i.e., it changed. If that happens in an alias group, the assembly output would prefer a different alias for no apparent good reasons. A way to fix that is to use proper priority for all aliases, but we can also make the tie breaker comparison smarter and use a deterministic ordering. This is what this patch does. llvm-svn: 294695
* Revert r294437 as it broke an asan buildbot.Amara Emerson2017-02-081-7/+2
| | | | llvm-svn: 294523
* [AArch64][TableGen] Skip tied result operands for InstAliasAmara Emerson2017-02-081-2/+7
| | | | | | | | | | | | | | | | | | | | | | | This patch checks the number of operands in the resulting instruction instead of just the alias, then skips over tied operands when generating the printing method. This allows us to generate the preferred assembly syntax for the AArch64 'ins' instruction, which should always be displayed as 'mov' according to the ARMARM. Several unit tests have changed as a result, but only to reflect the preferred disassembly. Some other InstAlias patterns (movk/bic/orr) needed a slight adjustment to stop them becoming the default and breaking other unit tests. Patch by Graham Hunter. Differential Revision: https://reviews.llvm.org/D29219 llvm-svn: 294437
* Mark comparator call operator as constEric Fiselier2016-12-271-1/+1
| | | | llvm-svn: 290636
* TableGen: Use StringRef instead of const std::string& in return vals.Matthias Braun2016-12-041-9/+9
| | | | | | | This will allow to switch to a different string storage in an upcoming commit. llvm-svn: 288612
* Fix some Clang-tidy and Include What You Use warnings; other minor fixes (NFC).Eugene Zelenko2016-11-301-18/+37
| | | | | | This preparation to remove SetVector.h dependency on SmallSet.h. llvm-svn: 288256
* TableGen: Allow signed immediates for instruction aliasesJacob Baungard Hansen2016-11-241-1/+1
| | | | | | | | | | | | Patch by Daniel Cederman. Reviewers: stoklund, arsenm Subscribers: arsenm, llvm-commits Differential Revision: https://reviews.llvm.org/D27046 llvm-svn: 287856
* [tablegen] Merge duplicate definitions of getMinimalTypeForRange. NFC.Daniel Sanders2016-11-191-10/+2
| | | | | | | | | | | | Summary: Depends on D25614 Reviewers: qcolombet Subscribers: qcolombet, beanz, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D25617 llvm-svn: 287438
* Use the range variant of remove_if instead of unpacking begin/endDavid Majnemer2016-08-121-4/+2
| | | | | | No functionality change is intended. llvm-svn: 278475
* Use the range variant of find/find_if instead of unpacking begin/endDavid Majnemer2016-08-121-5/+3
| | | | | | | | | If the result of the find is only used to compare against end(), just use is_contained instead. No functionality change is intended. llvm-svn: 278469
* TableGen: promote "code" type from syntactic sugar.Tim Northover2016-07-051-1/+1
| | | | | | | It's being immediately converted to a "string", but being able to tell what type the field was originally can be useful in backends. llvm-svn: 274575
* Run clang-tidy's performance-unnecessary-copy-initialization over LLVM.Benjamin Kramer2016-06-121-1/+1
| | | | | | No functionality change intended. llvm-svn: 272516
* AsmWriterEmitter.cpp assumes that all operands of a printed aliasSjoerd Meijer2016-06-031-3/+4
| | | | | | | | | | | will appear after a blank. This assumption does not hold in the ARM target. Patch by: Roger Ferrer Ibanez Differential Revision: http://reviews.llvm.org/D20234 llvm-svn: 271666
* Currently AsmWriterEmiter.cpp (used by tblgen -gen-asm-writer) does notSjoerd Meijer2016-06-031-2/+34
| | | | | | | | | | | | | consider the Predicates attached to InstAlias when generating printAliasInstr. This forces users of printAliasInstr to check those predicates beforehand. This commit adds them in the condition set of the IAPrinter object. Patch by: Roger Ferrer Ibanez Differential Revision: http://reviews.llvm.org/D20233 llvm-svn: 271665
* Apply clang-tidy's misc-move-constructor-init throughout LLVM.Benjamin Kramer2016-05-271-1/+3
| | | | | | No functionality change intended, maybe a tiny performance improvement. llvm-svn: 270997
* Fix commentXinliang David Li2016-02-231-1/+1
| | | | llvm-svn: 261672
* [TableGen] In AsmWriterEmitter unique command search, rather than storing a ↵Craig Topper2016-01-241-43/+32
| | | | | | | | mapping from instruction to unique command, instead store a list of which instructions each unique command corresponds to. This simplifies the complexity of the code that tries to find further operands to merge into the unique command. llvm-svn: 258656
* [TableGen] Make a class member local to the function that populates it and ↵Craig Topper2016-01-221-1/+2
| | | | | | consumes it later. NFC llvm-svn: 258490
* [TableGen] Keep a returned const reference instead of making a copy. NFCCraig Topper2016-01-171-1/+1
| | | | llvm-svn: 258020
* [TableGen] Return ArrayRef instead of a std::vector reference from ↵Craig Topper2016-01-171-7/+7
| | | | | | getInstructionsByEnumValue(). NFC llvm-svn: 258018
* [TableGen] Changes to AsmWriterEmitter to remove the CodeGenInstruction to ↵Craig Topper2016-01-171-67/+43
| | | | | | | | AsmWriterInst map. NFC Adds the corresponding CodeGenInstruction number to each AsmWriterInst. Then write all the operand uniqueing loops using the AsmWriterInst array and indices. Then use the CodeGenInstruction index to fill out the OpCodeInfo array. llvm-svn: 258005
* [TableGen] Use std::find instead of a manual loop. NFCCraig Topper2016-01-171-10/+8
| | | | llvm-svn: 258004
* [TableGen] Pass PassSubtarget flag into getCode instead of storing a copy of ↵Craig Topper2016-01-141-15/+18
| | | | | | the flag in every AsmWriterOperand. NFC llvm-svn: 257743
* [TableGen] Cleanup output formatting and add llvm_unreachables to the output ↵Craig Topper2016-01-131-5/+6
| | | | | | the AsmMatcher uses when it overflows the 64-bit tables. No in tree targets use this code, but I tested it with an temporarily reduced table width. llvm-svn: 257583
* [TableGen] Replace some hardcoded assumptions that the OpcodeInfo table is ↵Craig Topper2016-01-131-8/+10
| | | | | | 64-bits for cleanliness. NFC llvm-svn: 257582
* [TableGen] Use std::remove_if instead of an n^2 loop. NFCCraig Topper2016-01-131-8/+5
| | | | llvm-svn: 257581
* [TableGen] Fix up some stale comments in the AsmMatcher. NFCCraig Topper2016-01-131-4/+2
| | | | llvm-svn: 257580
* [TableGen] Move calls to getValueAsInt out of a loop since they aren't ↵Craig Topper2016-01-131-2/+3
| | | | | | simple functions. NFC llvm-svn: 257579
* [TableGen] Allow asm writer to use up to 3 OpInfo tables instead of 2. This ↵Craig Topper2016-01-111-30/+32
| | | | | | | | allows x86 to use 56 total bits made up of a 32-bit, 16-bit, and 8-bit table. Previously we were using 64 total bits. This saves 14K from the x86 table size. And saves space on other targets as well. llvm-svn: 257315
* [TableGen] Remove unnecessary 0 terminator from an array that only existed ↵Craig Topper2016-01-111-4/+0
| | | | | | to prevent ending an array with a comma. But that's perfectly legal and not something we need to prevent. NFC llvm-svn: 257314
* [TableGen] Use range-based for loops. Also fix one loop to not use some ↵Craig Topper2016-01-081-25/+20
| | | | | | index name as an outer loop. NFC llvm-svn: 257156
* [TableGen] Combine variable declaration and initialization. Move a string ↵Craig Topper2016-01-081-3/+2
| | | | | | into a vector instead of copying. NFC llvm-svn: 257155
* [TableGen] Correct Namespace lookup with AltNames in AsmWriterEmitterHal Finkel2015-12-111-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | AsmWriterEmitter will generate a getRegisterName function with an alternate register name index as its second argument if the target makes use of them. The enum of these values is generated in RegisterInfoEmitter. The getRegisterName generator would assume the namespace could always be found by reading index 1 of the list of AltNameIndices, but this will fail if this list is sorted such that the NoRegAltName is at index 1. Because this list is sorted by record name (in CodeGenTarget::ReadRegAltNameIndices), you only run in to problems if your MyTargetRegisterInfo.td defines a single RegAltNameIndex that sorts lexically before NoRegAltName. For example, if a target has something like def AnAltNameIndex : RegAltNameIndex and defines RegAltNameIndices for some registers then, prior to this change, AsmWriterEmitter would generate references to ::AnAltNameIndex and ::NoRegAltName Patch by Alex Bradbury! llvm-svn: 255344
* [AArch64] Add ARMv8.2-A Statistical Profiling ExtensionOliver Stannard2015-12-011-5/+7
| | | | | | | | | | | | The Statistical Profiling Extension is an optional extension to ARMv8.2-A. Since it is an optional extension, I have added the FeatureSPE subtarget feature to control it. The assembler-visible parts of this extension are the new "psb csync" instruction, which is equivalent to "hint #17", and a number of system registers. Differential Revision: http://reviews.llvm.org/D15021 llvm-svn: 254401
* Remove and forbid raw_svector_ostream::flush() calls.Yaron Keren2015-08-131-1/+0
| | | | | | | | | | After r244870 flush() will only compare two null pointers and return, doing nothing but wasting run time. The call is not required any more as the stream and its SmallString are always in sync. Thanks to David Blaikie for reviewing. llvm-svn: 244928
* Fix memory leaks by avoiding extra manual dynamic allocationDavid Blaikie2015-08-061-57/+41
| | | | | | Improvement to r244212. llvm-svn: 244252
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