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* [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca.Andrea Di Biagio2018-06-041-13/+27
| | | | | | | | | | | | | | | | | | | | | | | | This patch is the last of a sequence of three patches related to LLVM-dev RFC "MC support for variant scheduling classes". http://lists.llvm.org/pipermail/llvm-dev/2018-May/123181.html This fixes PR36672. The main goal of this patch is to teach llvm-mca how to solve variant scheduling classes. This patch does that, plus it adds new variant scheduling classes to the BtVer2 scheduling model to identify so-called zero-idioms (i.e. so-called dependency breaking instructions that are known to generate zero, and that are optimized out in hardware at register renaming stage). Without the BtVer2 change, this patch would not have had any meaningful tests. This patch is effectively the union of two changes: 1) a change that teaches llvm-mca how to resolve variant scheduling classes. 2) a change to the BtVer2 scheduling model that allows us to special-case packed XOR zero-idioms (this partially fixes PR36671). Differential Revision: https://reviews.llvm.org/D47374 llvm-svn: 333909
* [llvm-mca] Track cycles contributed by resources that are in a 'Super' ↵Andrea Di Biagio2018-06-041-1/+19
| | | | | | | | | | | | | | relationship. This is required if we want to correctly match the behavior of method SubtargetEmitter::ExpandProcResource() in Tablegen. When computing the set of "consumed" processor resources and resource cycles, the logic in ExpandProcResource() doesn't update the number of resource cycles contributed by a "Super" resource to a group. We need to take this into account when a model declares a processor resource which is part of a 'processor resource group', and it is also used as the "Super" of other resources. llvm-svn: 333892
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-11/+11
| | | | | | | | | | | | | | | | The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
* [llvm-mca] use colors for warnings and notes generated by InstrBuilder.Andrea Di Biagio2018-05-041-8/+9
| | | | llvm-svn: 331517
* [llvm-mca] remove unused argument from method InstrBuilder::createInstrDescImpl.Andrea Di Biagio2018-05-041-5/+6
| | | | | | | | | We don't need to pass the instruction index to the method that constructs new instruction descriptors. No functional change intended. llvm-svn: 331516
* [llvm-mca] Remove method Instruction::isZeroLatency(). NFCIAndrea Di Biagio2018-04-251-4/+3
| | | | llvm-svn: 330807
* [llvm-mca] Do not assume that implicit reads cannot be associated with ↵Andrea Di Biagio2018-04-021-4/+14
| | | | | | | | | | ReadAdvance entries. Before, the instruction builder incorrectly assumed that only explicit reads could have been associated with ReadAdvance entries. This patch fixes the issue and adds a test to verify it. llvm-svn: 328972
* [tools] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-04-011-10/+10
| | | | | | | | | | | | | | | | | | | | | | Summary: r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer the comments section in D44363 for a list of all the required patches. Reviewers: JDevlieghere, zturner, echristo, dberris, friss Reviewed By: echristo Subscribers: gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D45141 llvm-svn: 328943
* [llvm-mca] Correctly set the ReadAdvance information for register use operands.Andrea Di Biagio2018-03-291-0/+2
| | | | | | | | | | | | The tool was passing the wrong operand index to method MCSubtargetInfo::getReadAdvanceCycles(). That method requires a "UseIdx", and not the operand index. This was found when testing X86 code where instructions had a memory folded operand. This patch fixes the issue and adds test read-advance-1.s to ensure that the ReadAfterLd (a ReadAdvance of 3cy) information is correctly used. llvm-svn: 328790
* [llvm-mca] run clang-format on all files.Andrea Di Biagio2018-03-241-4/+4
| | | | | | This also addresses Simon's review comment in D44839. llvm-svn: 328428
* [llvm-mca] Simplify code. NFCAndrea Di Biagio2018-03-221-6/+4
| | | | llvm-svn: 328187
* [llvm-mca] Remove const from a bunch of ArrayRef. NFCAndrea Di Biagio2018-03-201-1/+1
| | | | llvm-svn: 328018
* [llvm-mca] Use llvm::make_unique in a few places. NFCAndrea Di Biagio2018-03-201-17/+13
| | | | | | Also, clang-format a couple of DEBUG functions. llvm-svn: 327978
* [llvm-mca] Move the routine that computes processor resource masks to its ↵Andrea Di Biagio2018-03-201-9/+6
| | | | | | | | | | | | | | | | | | own file. Function computeProcResourceMasks is used by the ResourceManager (owned by the Scheduler) to compute resource masks for processor resources. Before this refactoring, there was an implicit dependency between the Scheduler and the InstrBuilder. That is because InstrBuilder has to know about resource masks when computing the set of processor resources consumed by a new instruction. With this patch, the functionality that computes resource masks has been extracted from the ResourceManager, and moved to a separate file (Support.h). This helps removing the dependency between the Scheduler and the InstrBuilder. No functional change intended. llvm-svn: 327973
* [llvm-mca] Remove unused variable from InstrBuilder.cpp. NFCAndrea Di Biagio2018-03-141-1/+0
| | | | | | This was causing a buildbot failure. llvm-svn: 327517
* [llvm-mca] Move the logic that updates the register files from InstrBuilder ↵Andrea Di Biagio2018-03-141-33/+3
| | | | | | | | | | | | | | | | | | | to DispatchUnit. NFCI Before this patch, the register file was always updated at instruction creation time. That means, new read-after-write dependencies, and new temporary registers were allocated at instruction creation time. This patch refactors the code in InstrBuilder, and move all the logic that updates the register file into the dispatch unit. We only want to update the register file when instructions are effectively dispatched (not before). This refactoring also helps removing a bad dependency between the InstrBuilder and the DispatchUnit. No functional change intended. llvm-svn: 327514
* [llvm-mca] Simplify code that computes the latency of an instruction inAndrea Di Biagio2018-03-131-30/+5
| | | | | | | | | InstrBuilder. NFCI This was possible because of r327406, which added function`computeInstrLatency` to MCSchedModel. llvm-svn: 327415
* [llvm-mca] LLVM Machine Code Analyzer.Andrea Di Biagio2018-03-081-0/+525
llvm-mca is an LLVM based performance analysis tool that can be used to statically measure the performance of code, and to help triage potential problems with target scheduling models. llvm-mca uses information which is already available in LLVM (e.g. scheduling models) to statically measure the performance of machine code in a specific cpu. Performance is measured in terms of throughput as well as processor resource consumption. The tool currently works for processors with an out-of-order backend, for which there is a scheduling model available in LLVM. The main goal of this tool is not just to predict the performance of the code when run on the target, but also help with diagnosing potential performance issues. Given an assembly code sequence, llvm-mca estimates the IPC (instructions per cycle), as well as hardware resources pressure. The analysis and reporting style were mostly inspired by the IACA tool from Intel. This patch is related to the RFC on llvm-dev visible at this link: http://lists.llvm.org/pipermail/llvm-dev/2018-March/121490.html Differential Revision: https://reviews.llvm.org/D43951 llvm-svn: 326998
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