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author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2018-03-20 12:25:54 +0000 |
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committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2018-03-20 12:25:54 +0000 |
commit | 4704f0386bb8a29edb5d014ef7c00ef1b82fe78d (patch) | |
tree | 0259e9d0987c641812784514b3e69858e3ab902f /llvm/tools/llvm-mca/InstrBuilder.cpp | |
parent | a713ebea2456be61281e7570106a842357ce43a1 (diff) | |
download | bcm5719-llvm-4704f0386bb8a29edb5d014ef7c00ef1b82fe78d.tar.gz bcm5719-llvm-4704f0386bb8a29edb5d014ef7c00ef1b82fe78d.zip |
[llvm-mca] Move the routine that computes processor resource masks to its own file.
Function computeProcResourceMasks is used by the ResourceManager (owned by the
Scheduler) to compute resource masks for processor resources. Before this
refactoring, there was an implicit dependency between the Scheduler and the
InstrBuilder. That is because InstrBuilder has to know about resource masks when
computing the set of processor resources consumed by a new instruction.
With this patch, the functionality that computes resource masks has been
extracted from the ResourceManager, and moved to a separate file (Support.h).
This helps removing the dependency between the Scheduler and the InstrBuilder.
No functional change intended.
llvm-svn: 327973
Diffstat (limited to 'llvm/tools/llvm-mca/InstrBuilder.cpp')
-rw-r--r-- | llvm/tools/llvm-mca/InstrBuilder.cpp | 15 |
1 files changed, 6 insertions, 9 deletions
diff --git a/llvm/tools/llvm-mca/InstrBuilder.cpp b/llvm/tools/llvm-mca/InstrBuilder.cpp index 8a0335c7fd8..1bf2b36be52 100644 --- a/llvm/tools/llvm-mca/InstrBuilder.cpp +++ b/llvm/tools/llvm-mca/InstrBuilder.cpp @@ -357,8 +357,7 @@ static void populateReads(InstrDesc &ID, const MCInst &MCI, } } -void InstrBuilder::createInstrDescImpl(const MCSubtargetInfo &STI, - const MCInst &MCI) { +void InstrBuilder::createInstrDescImpl(const MCInst &MCI) { assert(STI.getSchedModel().hasInstrSchedModel() && "Itineraries are not yet supported!"); @@ -410,17 +409,15 @@ void InstrBuilder::createInstrDescImpl(const MCSubtargetInfo &STI, Descriptors[Opcode] = std::unique_ptr<const InstrDesc>(ID); } -const InstrDesc &InstrBuilder::getOrCreateInstrDesc(const MCSubtargetInfo &STI, - const MCInst &MCI) { +const InstrDesc &InstrBuilder::getOrCreateInstrDesc(const MCInst &MCI) { auto it = Descriptors.find(MCI.getOpcode()); if (it == Descriptors.end()) - createInstrDescImpl(STI, MCI); + createInstrDescImpl(MCI); return *Descriptors[MCI.getOpcode()].get(); } -Instruction *InstrBuilder::createInstruction(const MCSubtargetInfo &STI, - unsigned Idx, const MCInst &MCI) { - const InstrDesc &D = getOrCreateInstrDesc(STI, MCI); +Instruction *InstrBuilder::createInstruction(unsigned Idx, const MCInst &MCI) { + const InstrDesc &D = getOrCreateInstrDesc(MCI); Instruction *NewIS = new Instruction(D); // Populate Reads first. @@ -446,7 +443,7 @@ Instruction *InstrBuilder::createInstruction(const MCSubtargetInfo &STI, assert(RegID > 0 && "Invalid register ID found!"); ReadState *NewRDS = new ReadState(RD, RegID); NewIS->getUses().emplace_back(std::unique_ptr<ReadState>(NewRDS)); - } + } // Now populate writes. for (const WriteDescriptor &WD : D.Writes) { |