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path: root/llvm/tools/llvm-mca/Dispatch.cpp
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* [llvm-mca] Make Dispatch a subclass of Stage.Matt Davis2018-05-171-151/+0
* [llvm-mca] Move the RegisterFile class into its own translation unit. NFCMatt Davis2018-05-161-236/+1
* [llvm-mca] Introduce a pipeline Stage class and FetchStage.Matt Davis2018-05-151-4/+3
* [llvm-mca] Improved support for dependency-breaking instructions.Andrea Di Biagio2018-05-141-18/+31
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-6/+7
* [llvm-mca] Avoid exposing index values in the MCA interfaces.Matt Davis2018-05-071-28/+26
* [llvm-mca] Lift the logic of the RetireControlUnit from the Dispatch translat...Matt Davis2018-05-011-70/+2
* [llvm-mca] Correctly handle zero-latency stores that consume pipeline resources.Andrea Di Biagio2018-04-301-1/+2
* [llvm-mca] run clang-format on a bunch of files. NFCAndrea Di Biagio2018-04-251-1/+2
* [llvm-mca] Remove method Instruction::isZeroLatency(). NFCIAndrea Di Biagio2018-04-251-3/+7
* [llvm-mca] Let the Scheduler notify dispatch stall events caused by the lack ...Andrea Di Biagio2018-04-111-21/+1
* [MC][Tablegen] Allow models to describe the retire control unit for llvm-mca. Andrea Di Biagio2018-04-051-0/+18
* [MC][Tablegen] Allow the definition of processor register files in the schedu...Andrea Di Biagio2018-04-031-49/+94
* [llvm-mca] Correctly set the ReadAdvance information for register use operands.Andrea Di Biagio2018-03-291-1/+1
* [llvm-mca] pass the correct set of used registers in checkRAT.Andrea Di Biagio2018-03-271-3/+5
* [llvm-mca] run clang-format on all files.Andrea Di Biagio2018-03-241-3/+2
* [llvm-mca] Simplify (and better standardize) the Instruction interface.Andrea Di Biagio2018-03-221-9/+9
* [llvm-mca] Move the logic that computes the register file usage to the Backen...Andrea Di Biagio2018-03-211-19/+22
* [llvm-mca] Clean up some code. NFCAndrea Di Biagio2018-03-211-13/+4
* [llvm-mca] Remove const from a bunch of ArrayRef. NFCAndrea Di Biagio2018-03-201-1/+1
* [llvm-mca] Simplify code. NFCAndrea Di Biagio2018-03-191-1/+1
* [llvm-mca] Add pipeline stall events.Andrea Di Biagio2018-03-191-32/+16
* [llvm-mca] Allow the definition of multiple register files.Andrea Di Biagio2018-03-181-44/+139
* [llvm-mca] Simplify code. NFC.Andrea Di Biagio2018-03-151-1/+2
* [llvm-mca] Move the logic that updates the register files from InstrBuilder t...Andrea Di Biagio2018-03-141-1/+42
* [llvm-mca] Refactor event listeners to make the backend agnostic to event types.Clement Courbet2018-03-131-3/+12
* [llvm-mca] Fix handling of zero-latency instructions.Andrea Di Biagio2018-03-081-0/+1
* [llvm-mca] LLVM Machine Code Analyzer.Andrea Di Biagio2018-03-081-0/+268
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