[llvm-mca] Lift the logic of the RetireControlUnit from the Dispatch translation unit into its own translation unit. NFC

The logic remains the same.  Eventually, I see the RCU acting as its own separate stage in the instruction pipeline.

Differential Revision: https://reviews.llvm.org/D46331

llvm-svn: 331316

1 files changed, 2 insertions, 70 deletions

diff --git a/llvm/tools/llvm-mca/Dispatch.cpp b/llvm/tools/llvm-mca/Dispatch.cpp
index 9bccca7dd36..4984485d882 100644
--- a/llvm/tools/llvm-mca/Dispatch.cpp
+++ b/llvm/tools/llvm-mca/Dispatch.cpp
@@ -8,8 +8,8 @@
 //===----------------------------------------------------------------------===//
 /// \file
 ///
-/// This file implements methods declared by class RegisterFile, DispatchUnit
-/// and RetireControlUnit.
+/// This file implements methods declared by class RegisterFile and
+/// DispatchUnit.
 ///
 //===----------------------------------------------------------------------===//
 
@@ -252,41 +252,6 @@ void RegisterFile::dump() const {
 }
 #endif
 
-RetireControlUnit::RetireControlUnit(const llvm::MCSchedModel &SM,
-                                     DispatchUnit *DU)
-    : NextAvailableSlotIdx(0), CurrentInstructionSlotIdx(0),
-      AvailableSlots(SM.MicroOpBufferSize), MaxRetirePerCycle(0), Owner(DU) {
-  // Check if the scheduling model provides extra information about the machine
-  // processor. If so, then use that information to set the reorder buffer size
-  // and the maximum number of instructions retired per cycle.
-  if (SM.hasExtraProcessorInfo()) {
-    const MCExtraProcessorInfo &EPI = SM.getExtraProcessorInfo();
-    if (EPI.ReorderBufferSize)
-      AvailableSlots = EPI.ReorderBufferSize;
-    MaxRetirePerCycle = EPI.MaxRetirePerCycle;
-  }
-
-  assert(AvailableSlots && "Invalid reorder buffer size!");
-  Queue.resize(AvailableSlots);
-}
-
-// Reserves a number of slots, and returns a new token.
-unsigned RetireControlUnit::reserveSlot(unsigned Index, unsigned NumMicroOps) {
-  assert(isAvailable(NumMicroOps));
-  unsigned NormalizedQuantity =
-      std::min(NumMicroOps, static_cast<unsigned>(Queue.size()));
-  // Zero latency instructions may have zero mOps. Artificially bump this
-  // value to 1. Although zero latency instructions don't consume scheduler
-  // resources, they still consume one slot in the retire queue.
-  NormalizedQuantity = std::max(NormalizedQuantity, 1U);
-  unsigned TokenID = NextAvailableSlotIdx;
-  Queue[NextAvailableSlotIdx] = {Index, NormalizedQuantity, false};
-  NextAvailableSlotIdx += NormalizedQuantity;
-  NextAvailableSlotIdx %= Queue.size();
-  AvailableSlots -= NormalizedQuantity;
-  return TokenID;
-}
-
 void DispatchUnit::notifyInstructionDispatched(unsigned Index,
                                                ArrayRef<unsigned> UsedRegs) {
   DEBUG(dbgs() << "[E] Instruction Dispatched: " << Index << '\n');
@@ -304,39 +269,6 @@ void DispatchUnit::notifyInstructionRetired(unsigned Index) {
   Owner->eraseInstruction(Index);
 }
 
-void RetireControlUnit::cycleEvent() {
-  if (isEmpty())
-    return;
-
-  unsigned NumRetired = 0;
-  while (!isEmpty()) {
-    if (MaxRetirePerCycle != 0 && NumRetired == MaxRetirePerCycle)
-      break;
-    RUToken &Current = Queue[CurrentInstructionSlotIdx];
-    assert(Current.NumSlots && "Reserved zero slots?");
-    if (!Current.Executed)
-      break;
-    Owner->notifyInstructionRetired(Current.Index);
-    CurrentInstructionSlotIdx += Current.NumSlots;
-    CurrentInstructionSlotIdx %= Queue.size();
-    AvailableSlots += Current.NumSlots;
-    NumRetired++;
-  }
-}
-
-void RetireControlUnit::onInstructionExecuted(unsigned TokenID) {
-  assert(Queue.size() > TokenID);
-  assert(Queue[TokenID].Executed == false && Queue[TokenID].Index != ~0U);
-  Queue[TokenID].Executed = true;
-}
-
-#ifndef NDEBUG
-void RetireControlUnit::dump() const {
-  dbgs() << "Retire Unit: { Total Slots=" << Queue.size()
-         << ", Available Slots=" << AvailableSlots << " }\n";
-}
-#endif
-
 bool DispatchUnit::checkRAT(unsigned Index, const Instruction &Instr) {
   SmallVector<unsigned, 4> RegDefs;
   for (const std::unique_ptr<WriteState> &RegDef : Instr.getDefs())