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* [mips][microMIPS] Revert commit r266861.Zoran Jovanovic2016-04-226-26/+7
| | | | | | Commit r266861 was the reason for failing tests in LLVM test suite. llvm-svn: 267166
* [Hexagon] Teach mux expansion how to deal with undef predicatesKrzysztof Parzyszek2016-04-221-0/+22
| | | | llvm-svn: 267165
* [Hexagon] Add definitions for trap/pause instructionsKrzysztof Parzyszek2016-04-221-0/+36
| | | | | | Also add tests for other instructions from HexagonSystemInst.td. llvm-svn: 267162
* [EarlyCSE] Don't add the overflow flags to the hashDavid Majnemer2016-04-221-3/+2
| | | | | | | | We take the intersection of overflow flags while CSE'ing. This permits us to consider two instructions with different overflow behavior to be replaceable. llvm-svn: 267153
* Emit code16 in assembly in 16-bit modeNirav Dave2016-04-221-0/+20
| | | | | | | | | | | | | | | Summary: When generating assembly using -m16 we must explicitly mark it as 16-bit. Emit .code16 at beginning of file. Fixes wrong results when using -fno-integrated-as. Reviewers: dwmw2 Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19392 llvm-svn: 267152
* [mips] Fix select patterns for MIPS64Simon Dardis2016-04-221-0/+50
| | | | | | | | | | | | | | When targetting MIPS64R6 some of the patterns for select were guarded by a broken predicate. The predicate was supposed to test if a constant value could fit in a 16 bit zero-extended field. Instead the value was tested to fit in a 16 bit sign-extended field. For negative constants of native word width this resulted in wrong code generation. Reviewers: vkalintiris, dsanders Differential Review: http://reviews.llvm.org/D19378 llvm-svn: 267151
* Revert r267049, r26706[16789], r267071 - Refactor raw pdb dumper into libraryDaniel Sanders2016-04-221-1/+1
| | | | | | r267049 broke multiple buildbots (e.g. clang-cmake-mips, and clang-x86_64-linux-selfhost-modules) which the follow-ups have not yet resolved and this is preventing subsequent committers from being notified about additional failures on the affected buildbots. llvm-svn: 267148
* AMDGPU/SI: Add test missed in rL266865Nikolay Haustov2016-04-221-0/+55
| | | | llvm-svn: 267144
* [InstCombine] Preserve fast math flags when combining PHIsSilviu Baranga2016-04-221-0/+89
| | | | | | | | | | | | | | | | | | | | Summary: When optimizing PHIs which have inputs floating point binary operators, we preserve all IR flags except the fast math flags. This change removes the logic which tracked some of the IR flags (no wrap, exact) and replaces it by doing an and on the IR flags of all inputs to the PHI - which will also handle the fast math flags. Reviewers: majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19370 llvm-svn: 267139
* [mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructionsHrvoje Varga2016-04-226-2/+18
| | | | | | Differential Revision: http://reviews.llvm.org/D19354 llvm-svn: 267137
* [mips][microMIPS] Add R_MICROMIPS_PC18_S3 relocationZoran Jovanovic2016-04-222-0/+9
| | | | | | Differential Revision: http://reviews.llvm.org/D15026 llvm-svn: 267130
* Revert r267098 - [MachineCombiner] Support for floating-point FMA on ARM64Daniel Sanders2016-04-222-264/+0
| | | | | | It introduced buildbot failures on clang-cmake-mips, clang-ppc64le-linux, among others. llvm-svn: 267127
* [X86]: Changing cost for “TRUNCATE v16i32 to v16i8” in SSE4.1 mode.Ashutosh Nema2016-04-221-1/+1
| | | | | | | | | | | | | | Summary: rL256194 transforms truncations between vectors of integers into PACKUS/PACKSS operations during DAG combine. This generates better code for truncate, so cost of truncate needs to be changed but looks like it got changed only in SSE2 table Whereas this change is also applicable for SSE4.1, so the cost of truncate needs to be changed for that as well. Cost of “TRUNCATE v16i32 to v16i8” & “TRUNCATE v16i16 to v16i8” should be same in SSE4.1 & SSE2 table. Removing their cost from SSE4.1, so it will fall back to SSE2. Reviewers: Simon Pilgrim llvm-svn: 267123
* Revert "Initial implementation of optimization bisect support."Vedant Kumar2016-04-223-296/+0
| | | | | | | | This reverts commit r267022, due to an ASan failure: http://lab.llvm.org:8080/green/job/clang-stage2-cmake-RgSan_check/1549 llvm-svn: 267115
* [mips][microMIPS] Implement DVP, EVP and JALRC.HB instructionsZlatko Buljan2016-04-226-0/+36
| | | | | | Differential Revision: http://reviews.llvm.org/D18687 llvm-svn: 267114
* [GVN] Respect fast-math-flags on fcmpsDavid Majnemer2016-04-221-0/+18
| | | | | | | We assumed that flags were only present on binary operators. This is not true, they may also be present on calls and fcmps. llvm-svn: 267113
* [EarlyCSE] Take the intersection of flags on instructionsDavid Majnemer2016-04-221-0/+18
| | | | | | | | | | | | | EarlyCSE had inconsistent behavior with regards to flag'd instructions: - In some cases, it would pessimize if the available instruction had different flags by not performing CSE. - In other cases, it would miscompile if it replaced an instruction which had no flags with an instruction which has flags. Fix this by being more consistent with our flag handling by utilizing andIRFlags. llvm-svn: 267111
* AMDGPU/SI: add llvm.amdgcn.ps.live intrinsicNicolai Haehnle2016-04-221-0/+59
| | | | | | | | | | | | | | | | | | | | | | | Summary: This intrinsic returns true if the current thread belongs to a live pixel and false if it belongs to a pixel that we are executing only for derivative computation. It will be used by Mesa to implement gl_HelperInvocation. Note that for pixels that are killed during the shader, this implementation also returns true, but it doesn't matter because those pixels are always disabled in the EXEC mask. This unearthed a corner case in the instruction verifier, which complained about a v_cndmask 0, 1, exec, exec<imp-use> instruction. That's stupid but correct code, so make the verifier accept it as such. Reviewers: arsenm, tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19191 llvm-svn: 267102
* [AVX512] Teach lowering to use vplzcntd/q to implement 128/256-bit ↵Craig Topper2016-04-223-2/+317
| | | | | | CTTZ_ZERO_UNDEF even without VLX support. We can just extend to 512-bits and extract like we do for CTLZ. llvm-svn: 267100
* [MachineCombiner] Support for floating-point FMA on ARM64Gerolf Hoflehner2016-04-222-0/+264
| | | | | | | | | | | | | | | | Evaluates fmul+fadd -> fmadd combines and similar code sequences in the machine combiner. It adds support for float and double similar to the existing integer implementation. The key features are: - DAGCombiner checks whether it should combine greedily or let the machine combiner do the evaluation. This is only supported on ARM64. - It gives preference to throughput over latency: the heuristic used is to combine always in loops. The targets decides whether the machine combiner should optimize for throughput or latency. - Supports for fmadd, f(n)msub, fmla, fmls patterns - On by default at O3 ffast-math llvm-svn: 267098
* Try to fix UNRESOLVED: LLVM :: CodeGen/AArch64/arm64-regress-opt-cmp.s on bots.Nico Weber2016-04-221-0/+1
| | | | | | | | This test used to write a .s file until r266971 fixed that. But on most bots, the .s file still exists. Add an rm statement to clean up the bots. In a few days, this statement can go away again. llvm-svn: 267095
* ARM: fix test for Windows divisionSaleem Abdulrasool2016-04-221-4/+4
| | | | | | | This was meant to be part of SVN r267080. cbz cannot use a high register, which would be silently truncated. This has now been fixed. llvm-svn: 267092
* [WebAssembly] Limit alignment hints to natural alignment.Dan Gohman2016-04-213-17/+21
| | | | | | This follows the current binary format rules. llvm-svn: 267082
* ARM: restrict register class for WIN__DBZCHKSaleem Abdulrasool2016-04-211-0/+47
| | | | | | | | | | | WIN__DBZCHK will insert a CBZ instruction into the stream. This instruction reserves 3 bits for the condition register (rn). As such, we must ensure that we restrict the register to a low register. Use the tGPR class instead of GPR to ensure that this is properly constrained. In debug builds, we would attempt to use lr as a condition register which would silently get truncated with no hint that the register selection was incorrect. llvm-svn: 267080
* [sancov] using normalized filenames for blacklist checks.Mike Aizatsky2016-04-2110-29/+28
| | | | | | Differential Revision: http://reviews.llvm.org/D19395 llvm-svn: 267078
* MachO: enable .data_region directives everywhereTim Northover2016-04-213-107/+96
| | | | | | | | | | We'd disabled them on x86 because back in the early days some host tools couldn't handle the new load commands. This no longer holds: anyone capable of deploying Clang should be able to deploy its copies of ar/ranlib/etc. rdar://25254790 llvm-svn: 267075
* Fix pdbdump-headers.test after guid format change.Zachary Turner2016-04-211-1/+1
| | | | llvm-svn: 267067
* [esan] EfficiencySanitizer instrumentation passDerek Bruening2016-04-211-0/+257
| | | | | | | | | | | | | | | | | | | | | | | Summary: Adds an instrumentation pass for the new EfficiencySanitizer ("esan") performance tuning family of tools. Multiple tools will be supported within the same framework. Preliminary support for a cache fragmentation tool is included here. The shared instrumentation includes: + Turn mem{set,cpy,move} instrinsics into library calls. + Slowpath instrumentation of loads and stores via callouts to the runtime library. + Fastpath instrumentation will be per-tool. + Which memory accesses to ignore will be per-tool. Reviewers: eugenis, vitalybuka, aizatsky, filcab Subscribers: filcab, vkalintiris, pcc, silvas, llvm-commits, zhaoqin, kcc Differential Revision: http://reviews.llvm.org/D19167 llvm-svn: 267058
* Fix a typo in an error message. Caught by Sean Silva!Kevin Enderby2016-04-211-2/+2
| | | | llvm-svn: 267056
* add tests for disguised fabs/fnegSanjay Patel2016-04-211-0/+29
| | | | llvm-svn: 267053
* use FileCheck; add test for disguised fabsSanjay Patel2016-04-211-4/+27
| | | | llvm-svn: 267051
* [Hexagon] Properly recognize register alt namesKrzysztof Parzyszek2016-04-211-0/+14
| | | | llvm-svn: 267038
* Folding compares with unescaped allocationsSanjoy Das2016-04-211-0/+42
| | | | | | | | | | | | | | | | Summary: If we know that the pointer allocated within a function does not escape, we can fold away comparisons that are done with global pointers Patch by Anna Thomas! Reviewers: reames, majnemer, sanjoy Subscribers: mgrang, mcrosier, majnemer, llvm-commits Differential Revision: http://reviews.llvm.org/D19276 llvm-svn: 267035
* [Hexagon] Expand handling of the small-data/bss sectionKrzysztof Parzyszek2016-04-215-5/+88
| | | | llvm-svn: 267034
* DAGCombiner: Reduce 64-bit BFE pattern to pattern on 32-bit componentMatt Arsenault2016-04-215-7/+515
| | | | | | | If the extracted bits are restricted to the upper half or lower half, this can be truncated. llvm-svn: 267024
* [instcombine][unordered] Extend load(select) transform to handle unordered loadsPhilip Reames2016-04-211-0/+28
| | | | llvm-svn: 267023
* Initial implementation of optimization bisect support.Andrew Kaylor2016-04-213-0/+296
| | | | | | | | | | | | This patch implements a optimization bisect feature, which will allow optimizations to be selectively disabled at compile time in order to track down test failures that are caused by incorrect optimizations. The bisection is enabled using a new command line option (-opt-bisect-limit). Individual passes that may be skipped call the OptBisect object (via an LLVMContext) to see if they should be skipped based on the bisect limit. A finer level of control (disabling individual transformations) can be managed through an addition OptBisect method, but this is not yet used. The skip checking in this implementation is based on (and replaces) the skipOptnoneFunction check. Where that check was being called, a new call has been inserted in its place which checks the bisect limit and the optnone attribute. A new function call has been added for module and SCC passes that behaves in a similar way. Differential Revision: http://reviews.llvm.org/D19172 llvm-svn: 267022
* [unordered] unordered loads from null are still unreachablePhilip Reames2016-04-211-0/+51
| | | | llvm-svn: 267019
* [PowerPC] [SSP] Fix stack guard load for 32-bit.Marcin Koscielnicki2016-04-211-1/+1
| | | | | | | | r266809 incorrectly used LD to load the stack guard, it should be LWZ. Differential Revision: http://reviews.llvm.org/D19358 llvm-svn: 267017
* [instcombine][unordered] Implement *-load forwarding for unordered atomicsPhilip Reames2016-04-211-2/+35
| | | | | | This builds on 266999 which made FindAvailableValue do the right thing. Tests included show the newly enabled transforms and those which disabled either due to conservatism or correctness requirements. llvm-svn: 267006
* Fixed Dwarf debug info emission to skip DILexicalBlockFile entries.Amjad Aboud2016-04-211-0/+161
| | | | | | | | Before this fix, DILexicalBlockFile entries were skipped only in some cases and were not in other cases. Differential Revision: http://reviews.llvm.org/D18724 llvm-svn: 267004
* [unordered] Add tests and conservative handling in support of future changes ↵Philip Reames2016-04-211-1/+47
| | | | | | | | [NFCI] This change adds a couple of test cases to make sure FindAvailableLoadedValue does the right thing. At the moment, the code added is dead, but separating it makes follow on changes far more obvious. llvm-svn: 266999
* Fix recursive -only-needed.Rafael Espindola2016-04-212-0/+19
| | | | | | We were assuming that only linkonce_odr GVs were lazy linked. llvm-svn: 266995
* [mips][microMIPS] Implement ldpc instructionZoran Jovanovic2016-04-212-0/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D15009 llvm-svn: 266990
* [mips][microMIPS] Add R_MICROMIPS_PC19_S2 relocationZoran Jovanovic2016-04-212-1/+16
| | | | | | Differential Revision: http://reviews.llvm.org/D14915 llvm-svn: 266988
* [mips][microMIPS] Add R_MICROMIPS_PC26_S1 relocationZoran Jovanovic2016-04-212-0/+47
| | | | | | Differential Revision: http://reviews.llvm.org/D14822 llvm-svn: 266985
* [mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructionsZlatko Buljan2016-04-216-0/+40
| | | | | | Differential Revision: http://reviews.llvm.org/D18855 llvm-svn: 266980
* [mips][microMIPS] Implement LL, SC, MOVEP, ROTR, ROTRV and SYSCALL ↵Zlatko Buljan2016-04-2112-0/+111
| | | | | | | | instructions and add tests for LWM32 and SWM32 Differential Revision: http://reviews.llvm.org/D19150 llvm-svn: 266977
* Updated a test not to produce an empty s-file.Evgeny Astigeevich2016-04-211-1/+1
| | | | llvm-svn: 266971
* [AArch64][CodeGen] Fix of PR27158: incorrect peephole optimization in ↵Evgeny Astigeevich2016-04-212-0/+64
| | | | | | | | | | | | | | | | AArch64InstrInfo::optimizeCompareInstr AArch64InstrInfo::optimizeCompareInstr has bug PR27158 which causes generation of incorrect code. A compare instruction is substituted with another instruction which does not produce the same flags as the original compare instruction. This patch contains: 1. Fix of the bug. 2. A regression test in MIR. 3. A new test to check that SUBS is replaced by SUB. Differential Revision: http://reviews.llvm.org/D18838 llvm-svn: 266969
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