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| author | Saleem Abdulrasool <compnerd@compnerd.org> | 2016-04-21 23:53:19 +0000 |
|---|---|---|
| committer | Saleem Abdulrasool <compnerd@compnerd.org> | 2016-04-21 23:53:19 +0000 |
| commit | a0288535408cb58797a27465fed838753fcc6238 (patch) | |
| tree | a766f9a8178548e22c681bf54ce5c186c3b7a96b /llvm/test | |
| parent | f07dd8d0a925dd8cbde7bb6198c1ba92446110ea (diff) | |
| download | bcm5719-llvm-a0288535408cb58797a27465fed838753fcc6238.tar.gz bcm5719-llvm-a0288535408cb58797a27465fed838753fcc6238.zip | |
ARM: restrict register class for WIN__DBZCHK
WIN__DBZCHK will insert a CBZ instruction into the stream. This instruction
reserves 3 bits for the condition register (rn). As such, we must ensure that
we restrict the register to a low register. Use the tGPR class instead of GPR
to ensure that this is properly constrained. In debug builds, we would attempt
to use lr as a condition register which would silently get truncated with no
hint that the register selection was incorrect.
llvm-svn: 267080
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/ARM/Windows/dbzchk.ll | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/Windows/dbzchk.ll b/llvm/test/CodeGen/ARM/Windows/dbzchk.ll index 90195450e8e..bb25527a9cc 100644 --- a/llvm/test/CodeGen/ARM/Windows/dbzchk.ll +++ b/llvm/test/CodeGen/ARM/Windows/dbzchk.ll @@ -142,3 +142,50 @@ attributes #0 = { optsize } ; CHECK-CFG: bl __rt_udiv ; CHECK-CFG: pop.w {{{.*}}, r11, pc} +; RUN: llc -O0 -mtriple thumbv7--windows-itanium -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-WIN__DBZCHK + +; long k(void); +; int l(void); +; int j(int i) { +; if (l() == -1) +; return 0; +; return k() % i; +; } + +declare arm_aapcs_vfpcc i32 @k() +declare arm_aapcs_vfpcc i32 @l() + +define arm_aapcs_vfpcc i32 @j(i32 %i) { +entry: + %retval = alloca i32, align 4 + %i.addr = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + %call = call arm_aapcs_vfpcc i32 @l() + %cmp = icmp eq i32 %call, -1 + br i1 %cmp, label %if.then, label %if.end + +if.then: + store i32 0, i32* %retval, align 4 + br label %return + +if.end: + %call1 = call arm_aapcs_vfpcc i32 @k() + %0 = load i32, i32* %i.addr, align 4 + %rem = srem i32 %call1, %0 + store i32 %rem, i32* %retval, align 4 + br label %return + +return: + %1 = load i32, i32* %retval, align 4 + ret i32 %1 +} + +; CHECK-WIN__DBZCHK-LABEL: j: +; CHECK-WIN__DBZCHK: cbz r{{[0-7]}}, .LBB +; CHECK-WIN__DBZCHK-NOT: cbz r8, .LBB +; CHECK-WIN__DBZCHK-NOT: cbz r9, .LBB +; CHECK-WIN__DBZCHK-NOT: cbz r10, .LBB +; CHECK-WIN__DBZCHK-NOT: cbz r11, .LBB +; CHECK-WIN__DBZCHK-NOT: cbz ip, .LBB +; CHECK-WIN__DBZCHK-NOT: cbz lr, .LBB + |
