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* DAGCombiner: Don't unnecessarily swap operands in ReassociateOpsMatt Arsenault2016-02-274-9/+42
| | | | | | | | | | | | | | | | | | In the case where op = add, y = base_ptr, and x = offset, this transform: (op y, (op x, c1)) -> (op (op x, y), c1) breaks the canonical form of add by putting the base pointer in the second operand and the offset in the first. This fix is important for the R600 target, because for some address spaces the base pointer and the offset are stored in separate register classes. The old pattern caused the ISel code for matching addressing modes to put the base pointer and offset in the wrong register classes, which required no-trivial code transformations to fix. llvm-svn: 262148
* Addition of tests to previous check-in. Tests for coprocessor register usage ↵Chris Dewhurst2016-02-271-0/+72
| | | | | | | | | | | | | | | | in Sparc. Previous check-in message was: The patch adds missing registers and instructions to complete all the registers supported by the Sparc v8 manual. These are all co-processor registers, with the exception of the floating-point deferred-trap queue register. Although these will not be lowered automatically by any instructions, it allows the use of co-processor instructions implemented by inline-assembly. Code Reviewed at http://reviews.llvm.org/D17133, with the exception of a very small change in brace placement in SparcInstrInfo.td, which was formerly causing a problem in the disassembly of the %fq register. llvm-svn: 262135
* [X86][AVX] vpermilvar.pd mask element indices only use bit1Simon Pilgrim2016-02-271-6/+6
| | | | llvm-svn: 262134
* The patch adds missing registers and instructions to complete all the ↵Chris Dewhurst2016-02-273-11/+34
| | | | | | | | | | | | | registers supported by the Sparc v8 manual. These are all co-processor registers, with the exception of the floating-point deferred-trap queue register. Although these will not be lowered automatically by any instructions, it allows the use of co-processor instructions implemented by inline-assembly. Code Reviewed at http://reviews.llvm.org/D17133, with the exception of a very small change in brace placement in SparcInstrInfo.td, which was formerly causing a problem in the disassembly of the %fq register. llvm-svn: 262133
* [X86][AVX] Added AVX1 target shuffle combine testsSimon Pilgrim2016-02-271-0/+69
| | | | llvm-svn: 262132
* [PM] Loosen the regex for the proxy template name even further to copeChandler Carruth2016-02-271-3/+3
| | | | | | with 'class' keywords in the template arguments and other silliness. llvm-svn: 262130
* [PM] Use a boring regex instead of explicitly naming the analysisChandler Carruth2016-02-271-3/+3
| | | | | | | | | | manager as some compilers print the typedef name and others print the "canonical" name of the underlying class template. This isn't really an important artifact of the test anyways so it seems fine to just loosen the test assertions here. llvm-svn: 262129
* [PM] Provide two templates for the two directionalities of analysisChandler Carruth2016-02-271-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | manager proxies and use those rather than repeating their definition four times. There are real differences between the two directions: outer AMs are const and don't need to have invalidation tracked. But every proxy in a particular direction is identical except for the analysis manager type and the IR unit they proxy into. This makes them prime candidates for nice templates. I've started introducing explicit template instantiation declarations and definitions as well because we really shouldn't be emitting all this everywhere. I'm going to go back and add the same for the other templates like this in a follow-up patch. I've left the analysis manager as an opaque type rather than using two IR units and requiring it to be an AnalysisManager template specialization. I think its important that users retain the ability to provide their own custom analysis management layer and provided it has the appropriate API everything should Just Work. llvm-svn: 262127
* DAGCombiner: Relax sqrt NaN folding checkMatt Arsenault2016-02-271-2/+14
| | | | | | This is OK for +0 since compares to +/-0 give the same result. llvm-svn: 262125
* AMDGPU: Add s_sleep intrinsicMatt Arsenault2016-02-271-0/+45
| | | | llvm-svn: 262120
* AMDGPU: Implement readcyclecounterMatt Arsenault2016-02-274-0/+73
| | | | | | | | | | This matches the behavior of the HSAIL clock instruction. s_realmemtime is used if the subtarget supports it, and falls back to s_memtime if not. Also introduces new intrinsics for each of s_memtime / s_memrealtime. llvm-svn: 262119
* [instrprof] Use __{start,stop}_SECNAME on PS4 too.Sean Silva2016-02-271-0/+4
| | | | | | | | | | | | | | | | | | | | | Summary: The PS4 linker seems to handle this fine. Hi David, it seems that indeed most ELF linkers support __{start,stop}_SECNAME, as our proprietary linker does as well. This follows the pattern of r250679 w.r.t. the testing. Maggie, Phillip, Paul: I've tested this with the PS4 SDK 3.5 toolchain prerelease and it seems to work fine. Reviewers: davidxl Subscribers: probinson, phillip.power, MaggieYi Differential Revision: http://reviews.llvm.org/D17672 llvm-svn: 262112
* [libFuzzer] don't emit callbacks to sanitizer run-time in ↵Kostya Serebryany2016-02-271-0/+1
| | | | | | -fsanitize-coverage=trace-pc mode; update libFuzzer doc for previous commit llvm-svn: 262110
* [LICM] Teach LICM how to handle cases where the alias set tracker wasChandler Carruth2016-02-271-0/+39
| | | | | | | | | | | | | | | | | | | | merged into a loop that was subsequently unrolled (or otherwise nuked). In this case it can't merge in the ASTs for any remaining nested loops, it needs to re-add their instructions dircetly. The fix is very isolated, but I've pulled the code for merging blocks into the AST into a single place in the process. The only behavior change is in the case which would have crashed before. This fixes a crash reported by Mikael Holmen on the list after r261316 restored much of the loop pass pipelining and allowed us to actually do this kind of nested transformation sequenc. I've taken that test case and further reduced it into the somewhat twisty maze of loops in the included test case. This does in fact trigger the bug even in this reduced form. llvm-svn: 262108
* [sancov] print_coverage_points command.Mike Aizatsky2016-02-271-0/+20
| | | | | | Differential Revision: http://reviews.llvm.org/D17670 llvm-svn: 262104
* [InstCombine] Be more conservative about removing stackrestoreReid Kleckner2016-02-271-1/+57
| | | | | | | We ended up removing a save/restore pair around an inalloca call, leading to a miscompile in Chromium. llvm-svn: 262095
* Revert r262092, caught LLD testsPaul Robinson2016-02-261-28/+0
| | | | llvm-svn: 262093
* [FileCheck] Abort if -NOT is combined with another suffix.Paul Robinson2016-02-261-0/+28
| | | | | | | | | Combinations of suffixes that look useful actually are ignored; complaining about them will avoid mistakes. Differential Revision: http://reviews.llvm.org/D17587 llvm-svn: 262092
* Fix a bug in isVectorReductionOp() in SelectionDAGBuilder.cpp that may cause ↵Cong Hou2016-02-261-0/+52
| | | | | | assertion failure on AArch64. llvm-svn: 262091
* [X86] Move an encoding test from CodeGen to MC. NFC.Ahmed Bougacha2016-02-262-44/+32
| | | | llvm-svn: 262089
* [X86] Delete old redundant test. NFC.Ahmed Bougacha2016-02-261-12/+0
| | | | llvm-svn: 262088
* [LVI] Extend select handling to catch min/max/clamp idiomsPhilip Reames2016-02-261-0/+193
| | | | | | | | | | Most of this is fairly straight forward. Add handling for min/max via existing matcher utility and ConstantRange routines. Add handling for clamp by exploiting condition constraints on inputs. Note that I'm only handling two constant ranges at this point. It would be reasonable to consider treating overdefined as a full range if the instruction is typed as an integer, but that should be a separate change. Differential Revision: http://reviews.llvm.org/D17184 llvm-svn: 262085
* [PPC] Legalize FNEG on PPC when possibleKit Barton2016-02-261-2/+31
| | | | | | | | Currently we always expand ISD::FNEG. For v4f32 and v2f64 vector types VSX has native support for this opcode Phabricator: http://reviews.llvm.org/D17647 llvm-svn: 262079
* [x86, InstCombine] transform x86 AVX2 masked stores to LLVM intrinsicsSanjay Patel2016-02-261-0/+50
| | | | | | | | | Replicate everything for integers...because x86. Continuation of: http://reviews.llvm.org/rL262064 llvm-svn: 262077
* Reapply r262054 with triple fix.Paul Robinson2016-02-261-15/+15
| | | | llvm-svn: 262069
* Power9] Implement new vsx instructions: compare and conversionKit Barton2016-02-262-0/+196
| | | | | | | | | | | | | | | | | | | This change implements the following vsx instructions: Quad/Double-Precision Compare: xscmpoqp xscmpuqp xscmpexpdp xscmpexpqp xscmpeqdp xscmpgedp xscmpgtdp xscmpnedp xvcmpnedp(.) xvcmpnesp(.) Quad-Precision Floating-Point Conversion xscvqpdp(o) xscvdpqp xscvqpsdz xscvqpswz xscvqpudz xscvqpuwz xscvsdqp xscvudqp xscvdphp xscvhpdp xvcvhpsp xvcvsphp xsrqpi xsrqpix xsrqpxp 28 instructions Phabricator: http://reviews.llvm.org/D16709 llvm-svn: 262068
* [x86, InstCombine] transform x86 AVX masked stores to LLVM intrinsicsSanjay Patel2016-02-261-0/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The intended effect of this patch in conjunction with: http://reviews.llvm.org/rL259392 http://reviews.llvm.org/rL260145 is that customers using the AVX intrinsics in C will benefit from combines when the store mask is constant: void mstore_zero_mask(float *f, __m128 v) { _mm_maskstore_ps(f, _mm_set1_epi32(0), v); } void mstore_fake_ones_mask(float *f, __m128 v) { _mm_maskstore_ps(f, _mm_set1_epi32(1), v); } void mstore_ones_mask(float *f, __m128 v) { _mm_maskstore_ps(f, _mm_set1_epi32(0x80000000), v); } void mstore_one_set_elt_mask(float *f, __m128 v) { _mm_maskstore_ps(f, _mm_set_epi32(0x80000000, 0, 0, 0), v); } ...so none of the above will actually generate a masked store for optimized code. Differential Revision: http://reviews.llvm.org/D17485 llvm-svn: 262064
* Revert r262054 on one file that fails sometimes.Paul Robinson2016-02-261-14/+14
| | | | llvm-svn: 262060
* Fix tests that used CHECK-NEXT-NOT and CHECK-DAG-NOT.Paul Robinson2016-02-2612-31/+37
| | | | | | | | FileCheck actually doesn't support combo suffixes. Differential Revision: http://reviews.llvm.org/D17588 llvm-svn: 262054
* Fix Sparc 32bit Lowering to rebundle up v2i32 values.Nirav Dave2016-02-261-0/+33
| | | | | | | | | | | | Summary: Fix LowerCall to rebundle v2i32 values after lowering and add testcase Reviewers: jyknight Subscribers: llvm-commits, jyknight Differential Revision: http://reviews.llvm.org/D17615 llvm-svn: 262048
* [x86, AVX] fold 'isPositive' 256-bit vector integer operations (PR26701)Sanjay Patel2016-02-261-10/+4
| | | | | | | This extends the fold introduced with: http://reviews.llvm.org/rL262036 llvm-svn: 262047
* [x86, AVX] add 256-bit testsSanjay Patel2016-02-261-0/+136
| | | | llvm-svn: 262044
* [x86, SSE] fold 'isPositive' vector integer operations (PR26701)Sanjay Patel2016-02-261-37/+79
| | | | | | | | | | | | | This is one of the cases shown in: https://llvm.org/bugs/show_bug.cgi?id=26701 Shift and negate is what InstCombine appears to prefer, so I've started with that pattern. Note that the 'pcmpeq' instructions are always generating the negative one for the actual 'pcmpgt' comparison in each case (side note: why isn't there an alias mnemonic for that?). Differential Revision: http://reviews.llvm.org/D17630 llvm-svn: 262036
* [WinEH] Fix funclet return block clobber mask placementReid Kleckner2016-02-261-0/+73
| | | | | | | | | | | | | | | | | | MBB slot index intervals are half open, not closed. getMBBEndIndex() returns the slot index of the start of the next block in layout order. Placing a register mask there is incorrect if the successor of the funclet return is not laid out after the return. Clang generates IR for catch bodies before generating the following normal code, so we never noticed this issue until the D frontend authors filed a bug about it. Instead, we can put the clobber mask on the last instruction of the funclet return block. We still aren't using a register mask operand on the CATCHRET instruction because it would cause PEI to spill all CSRs, including XMM regs, in the prologue. Fixes PR26679. llvm-svn: 262035
* Reverting breaking change. Sorry.Chris Dewhurst2016-02-262-31/+11
| | | | llvm-svn: 262007
* Reviewed at reviews.llvm.org/D17133Chris Dewhurst2016-02-262-11/+31
| | | | llvm-svn: 262005
* [PM] Introduce CRTP mixin base classes to help define passes andChandler Carruth2016-02-261-1/+1
| | | | | | | | | | | | | | | | | analyses in the new pass manager. These just handle really basic stuff: turning a type name into a string statically that is nice to print in logs, and getting a static unique ID for each analysis. Sadly, the format of passes in anonymous namespaces makes using their names in tests really annoying so I've customized the names of the no-op passes to keep tests sane to read. This is the first of a few simplifying refactorings for the new pass manager that should reduce boilerplate and confusion. llvm-svn: 262004
* [AMDGPU] Assembler: Basic support for MIMGNikolay Haustov2016-02-2611-104/+119
| | | | | | | | | | | Add parsing and printing of image operands. Matches legacy sp3 assembler. Change image instruction order to have data/image/sampler operands in the beginning. This is needed because optional operands in MC are always last. Update SITargetLowering for new order. Add basic MC test. Update CodeGen tests. Review: http://reviews.llvm.org/D17574 llvm-svn: 261995
* [X86][F16C] Added native IR half/float conversion tests.Simon Pilgrim2016-02-261-0/+1760
| | | | | | Placeholder tests until we start improving native vector support. llvm-svn: 261989
* llvm-dwp: provide diagnostics for duplicate DWO IDsDavid Blaikie2016-02-264-0/+18
| | | | | | | | | | | | | | These diagnostics aren't perfect - in the case of merging several dwos into dwps and those dwps into more dwps - just getting the message about the original source file name might not be much help (since it's the same in both dwos, by definition - but doesn't tell you which chain of dwps to backtrack) It might be worth adding the DW_AT_dwo_id to the split debug info to improve the diagnostic experience - might help track down the duplicates better. llvm-svn: 261988
* llvm-dwp: Support empty .dwo filesDavid Blaikie2016-02-262-0/+8
| | | | | | | | | Though a bit odd, this is handy for a few reasons - for example, in a build system that wants consistent input/output of build steps, but where split-dwarf might be overriden/disabled by the user on a per-file basis. llvm-svn: 261987
* [X86] Add test cases for r261977 and fix a grammatical error.Craig Topper2016-02-261-0/+4
| | | | llvm-svn: 261983
* [JumpThreading] Simplify Instructions first in ComputeValueKnownInPredecessors()Haicheng Wu2016-02-261-0/+50
| | | | | | This change tries to find more opportunities to thread over basic blocks. llvm-svn: 261981
* Another fix the testcase introduced by r261903 - Add the missing matchesHongbin Zheng2016-02-261-3/+3
| | | | llvm-svn: 261971
* MachineCopyPropagation: Catch copies of the form A<-B;A<-BMatthias Braun2016-02-263-9/+108
| | | | | | Differential Revision: http://reviews.llvm.org/D17475 llvm-svn: 261966
* MachineCopyPropagation: Keep scanning through instructions with regmasksMatthias Braun2016-02-261-4/+59
| | | | | | | | | | | | | | | | | | | | | | | This also simplifies the code by removing the overly conservative NoInterveningSideEffect() function. This function checked: - That the two copies belong to the same block: We only process one block at a time and clear our maps in between it is impossible to find a copy from a different block. - There is no terminator between the two copy instructions: This is not allowed anyway (the MachineVerifier would complain) - Does not have instructions with hasUnmodeledSideEffects() or isCall() set: Even for those instructuction we must have all clobbers/defs of registers explicit as an operand. If the register is explicitely clobbered we would never come to the point of checking for NoInterveningSideEffect() anyway. (I also checked this with a temporary build of the test-suite with all potentially failing conditions in NoInterveningSideEffect() turned into asserts) Differential Revision: http://reviews.llvm.org/D17474 llvm-svn: 261965
* [PGO] Add test case to ensure covmap section is not allocatable.Xinliang David Li2016-02-262-0/+9
| | | | | | Differential Revision: http://reviews.llvm.org/D17324 llvm-svn: 261959
* [sancov] Pruning full dominator blocks from instrumentation.Mike Aizatsky2016-02-261-0/+9
| | | | | | | | | | | | | | Summary: This is the first simple attempt to reduce number of coverage- instrumented blocks. If a basic block dominates all its successors, then its coverage information is useless to us. Ingore such blocks if santizer-coverage-prune-tree option is set. Differential Revision: http://reviews.llvm.org/D17626 llvm-svn: 261949
* [x86, SSE] add tests to show missing pcmp foldsSanjay Patel2016-02-261-0/+88
| | | | llvm-svn: 261948
* [WinEH] Don't remove unannotated inline-asm callsDavid Majnemer2016-02-261-0/+26
| | | | | | | | Inline-asm calls aren't annotated with funclet bundle operands because they don't throw and cannot be inlined through. We shouldn't require them to bear an funclet bundle operand. llvm-svn: 261942
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