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authorReid Kleckner <rnk@google.com>2016-02-26 16:53:19 +0000
committerReid Kleckner <rnk@google.com>2016-02-26 16:53:19 +0000
commit70c9bc71d4f1a5cceea67ce6724da9080d5e05fa (patch)
tree2feb27c63b7e48dfe51de89981cabdb6df9d4270 /llvm/test
parent68e15559b8c331a74f7b5a2a9b69b7b1d0d5bd48 (diff)
downloadbcm5719-llvm-70c9bc71d4f1a5cceea67ce6724da9080d5e05fa.tar.gz
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[WinEH] Fix funclet return block clobber mask placement
MBB slot index intervals are half open, not closed. getMBBEndIndex() returns the slot index of the start of the next block in layout order. Placing a register mask there is incorrect if the successor of the funclet return is not laid out after the return. Clang generates IR for catch bodies before generating the following normal code, so we never noticed this issue until the D frontend authors filed a bug about it. Instead, we can put the clobber mask on the last instruction of the funclet return block. We still aren't using a register mask operand on the CATCHRET instruction because it would cause PEI to spill all CSRs, including XMM regs, in the prologue. Fixes PR26679. llvm-svn: 262035
Diffstat (limited to 'llvm/test')
-rw-r--r--llvm/test/CodeGen/X86/catchret-regmask.ll73
1 files changed, 73 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/catchret-regmask.ll b/llvm/test/CodeGen/X86/catchret-regmask.ll
new file mode 100644
index 00000000000..1231172a7e9
--- /dev/null
+++ b/llvm/test/CodeGen/X86/catchret-regmask.ll
@@ -0,0 +1,73 @@
+; RUN: llc < %s | FileCheck %s
+
+target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc"
+
+declare i32 @__CxxFrameHandler3(...)
+declare void @throw() noreturn uwtable
+declare i8* @getval()
+
+define i8* @reload_out_of_pad(i8* %arg) #0 personality i32 (...)* @__CxxFrameHandler3 {
+assertPassed:
+ invoke void @throw()
+ to label %unreachable unwind label %catch.dispatch
+
+catch:
+ %cp = catchpad within %cs [i8* null, i32 0, i8* null]
+ catchret from %cp to label %return
+
+ ; This block *must* appear after the catchret to test the bug.
+ ; FIXME: Make this an MIR test so we can control MBB layout.
+unreachable:
+ unreachable
+
+catch.dispatch:
+ %cs = catchswitch within none [label %catch] unwind to caller
+
+return:
+ ret i8* %arg
+}
+
+; CHECK-LABEL: reload_out_of_pad: # @reload_out_of_pad
+; CHECK: movq %rcx, -[[arg_slot:[0-9]+]](%rbp) # 8-byte Spill
+; CHECK: callq throw
+; CHECK: ud2
+; CHECK: movq -[[arg_slot]](%rbp), %rax # 8-byte Reload
+; CHECK: retq
+
+; CHECK: "?catch$3@?0?reload_out_of_pad@4HA":
+; CHECK-NOT: Reload
+; CHECK: retq
+
+define i8* @spill_in_pad() #0 personality i32 (...)* @__CxxFrameHandler3 {
+assertPassed:
+ invoke void @throw()
+ to label %unreachable unwind label %catch.dispatch
+
+catch:
+ %cp = catchpad within %cs [i8* null, i32 0, i8* null]
+ %val = call i8* @getval() [ "funclet"(token %cp) ]
+ catchret from %cp to label %return
+
+unreachable:
+ unreachable
+
+catch.dispatch:
+ %cs = catchswitch within none [label %catch] unwind to caller
+
+return:
+ ret i8* %val
+}
+
+; CHECK-LABEL: spill_in_pad: # @spill_in_pad
+; CHECK: callq throw
+; CHECK: ud2
+; CHECK: movq -[[val_slot:[0-9]+]](%rbp), %rax # 8-byte Reload
+; CHECK: retq
+
+; CHECK: "?catch$3@?0?spill_in_pad@4HA":
+; CHECK: callq getval
+; CHECK: movq %rax, -[[val_slot]](%rbp) # 8-byte Spill
+; CHECK: retq
+
+attributes #0 = { uwtable }
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