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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-02-27 09:38:05 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-02-27 09:38:05 +0000 |
| commit | 360d244d5befb9b8270d93a4aa0e3f0744c796e1 (patch) | |
| tree | 637ca80707fe6fa9fdfa780e6d6b3fd83a357727 /llvm/test | |
| parent | 5e020b2628522d086bb49bcc80f8f4ac0c978d8b (diff) | |
| download | bcm5719-llvm-360d244d5befb9b8270d93a4aa0e3f0744c796e1.tar.gz bcm5719-llvm-360d244d5befb9b8270d93a4aa0e3f0744c796e1.zip | |
DAGCombiner: Relax sqrt NaN folding check
This is OK for +0 since compares to +/-0 give the same result.
llvm-svn: 262125
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.sqrt.ll | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.sqrt.ll b/llvm/test/CodeGen/AMDGPU/llvm.sqrt.ll index c6da047f539..c8ac196e659 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.sqrt.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.sqrt.ll @@ -50,10 +50,10 @@ entry: ret void } -; SI-LABEL: {{^}}elim_redun_check: +; SI-LABEL: {{^}}elim_redun_check_neg0: ; SI: v_sqrt_f32_e32 ; SI-NOT: v_cndmask -define void @elim_redun_check(float addrspace(1)* %out, float %in) { +define void @elim_redun_check_neg0(float addrspace(1)* %out, float %in) { entry: %sqrt = call float @llvm.sqrt.f32(float %in) %cmp = fcmp olt float %in, -0.000000e+00 @@ -62,6 +62,18 @@ entry: ret void } +; SI-LABEL: {{^}}elim_redun_check_pos0: +; SI: v_sqrt_f32_e32 +; SI-NOT: v_cndmask +define void @elim_redun_check_pos0(float addrspace(1)* %out, float %in) { +entry: + %sqrt = call float @llvm.sqrt.f32(float %in) + %cmp = fcmp olt float %in, 0.000000e+00 + %res = select i1 %cmp, float 0x7FF8000000000000, float %sqrt + store float %res, float addrspace(1)* %out + ret void +} + ; SI-LABEL: {{^}}elim_redun_check_ult: ; SI: v_sqrt_f32_e32 ; SI-NOT: v_cndmask |
