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* [Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.Colin LeMahieu2015-06-0511-105/+41
| | | | llvm-svn: 239161
* [ARM] Add support for -sp- FPUs and FPU none to TargetParserJohn Brawn2015-06-052-4/+20
| | | | | | | | | | These are added mainly for the benefit of clang, but this also means that they are now allowed in .fpu directives and we emit the correct .fpu directive when single-precision-only is used. Differential Revision: http://reviews.llvm.org/D10238 llvm-svn: 239151
* [X86][AVX2] Added tests for v32i8 vector shiftsSimon Pilgrim2015-06-051-0/+390
| | | | | | Currently still scalarized, but D9474 should remedy that. llvm-svn: 239146
* Revert "[mips] [IAS] Restore STI.FeatureBits in .set pop." (r239144).Toma Tabacu2015-06-052-26/+0
| | | | | | This is breaking the Windows buildbots. llvm-svn: 239145
* [mips] [IAS] Restore STI.FeatureBits in .set pop.Toma Tabacu2015-06-052-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Only restoring AvailableFeatures is not enough and will lead to buggy behaviour. For example, if we have a feature enabled and we ".set pop", the next time we try to ".set" that feature nothing will happen because the "!(STI.getFeatureBits()[Feature])" check will be false, because we didn't restore STI.FeatureBits. In order to fix this, we need to make MipsAssemblerOptions remember the STI.FeatureBits instead of the AvailableFeatures and then regenerate AvailableFeatures each time we ".set pop". This is because, AFAIK, there is no way to convert from AvailableFeatures back to STI.FeatureBits, but the reverse is possible by using ComputeAvailableFeatures(STI.FeatureBits). I also moved the updating of AssemblerOptions inside the "if" statement in setFeatureBits() and clearFeatureBits(), as there is no reason to update if nothing changes. Reviewers: dsanders, mkuper Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9156 llvm-svn: 239144
* [LoopVectorize] Don't crash on zero-sized types in isInductionPHIDavid Majnemer2015-06-051-0/+27
| | | | | | | | | isInductionPHI wants to calculate the stride based on the pointee size. However, this is not possible when the pointee is zero sized. This fixes PR23763. llvm-svn: 239143
* Simplify code; NFC.Andrea Di Biagio2015-06-052-47/+48
| | | | | | | | Also, moved test cases from CodeGen/X86/fold-buildvector-bug.ll into CodeGen/X86/buildvec-insertvec.ll and regenerated CHECK lines using update_llc_test_checks.py. llvm-svn: 239142
* [InstCombine] Rephrase fix to SimplifyWithOpReplacedDavid Majnemer2015-06-051-0/+10
| | | | | | | | | | | | | | | | | | I don't have the IR which is causing the build bot breakage but I can postulate as to why they are timing out: 1. SimplifyWithOpReplaced was stripping flags from the simplified value. 2. visitSelectInstWithICmp was overriding SimplifyWithOpReplaced because it's simplification wasn't correct. 3. InstCombine would revisit the add instruction and note that it can rederive the flags. 4. By modifying the value, we chose to revisit instructions which reuse the value. One of the instructions is the original select, causing LLVM to never reach fixpoint. Instead, strip the flags only when we are sure we are going to perform the simplification. llvm-svn: 239141
* Revert "[InstCombine] Don't miscompile safe increment idiom"Daniel Jasper2015-06-051-10/+0
| | | | | | | | | This is breaking a lot of build bots and is causing very long-running compiles (infinite loops)? Likely, we shouldn't return nullptr? llvm-svn: 239139
* [X86][SSE] Added tests for i8/i16 vector shiftsSimon Pilgrim2015-06-051-0/+1016
| | | | | | Currently still scalarized, but D9474 should remedy that. llvm-svn: 239136
* Revert "[Object, ELF] Fix segmentation fault in ELFFile::getSectionName()."Alexey Samsonov2015-06-042-3/+0
| | | | | | This reverts commit r239124. llvm-svn: 239125
* [Object, ELF] Fix segmentation fault in ELFFile::getSectionName().Alexey Samsonov2015-06-042-0/+3
| | | | | | Don't do a null dereference if .shstrtab section is missing. llvm-svn: 239124
* [Object, ELF] Don't assert on invalid magic in createELFObjectFile.Alexey Samsonov2015-06-042-0/+2
| | | | | | Instead, return a proper error code from factory. llvm-svn: 239116
* [InstCombine] Don't miscompile safe increment idiomDavid Majnemer2015-06-041-0/+10
| | | | | | | | | | | We cleverly handle cases where computation done in one argument of a select instruction is suitable for the other operand, thus obviating the need of the select and the comparison. However, the other operand cannot have flags. This fixes PR23757. llvm-svn: 239115
* Statepoint: Fix handling of Far Immediate callsSwaroop Sridhar2015-06-041-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | gc.statepoint intrinsics with a far immediate call target were lowered incorrectly as pc-rel32 calls. This change fixes the problem, and generates an indirect call via a scratch register. For example: Intrinsic: %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* inttoptr (i64 140727162896504 to void ()*), i32 0, i32 0, i32 0, i32 0) Old Incorrect Lowering: callq 140727162896504 New Correct Lowering: movabsq $140727162896504, %rax callq *%rax In lowerCallFromStatepoint(), the callee-target was modified and represented as a "TargetConstant" node, rather than a "Constant" node. Undoing this modification enabled LowerCall() to generate the correct CALL instruction. llvm-svn: 239114
* [Object, ELF] Don't call llvm_unreachable() from createELFObjectFile.Alexey Samsonov2015-06-042-0/+2
| | | | | | Instead, return a proper error code from factory. llvm-svn: 239113
* [Target/X86] Don't use callee-saved registers in a Win64 tail call on ↵Charles Davis2015-06-041-0/+24
| | | | | | | | | | | | | | | | | | | | | | non-Windows. Summary: A small bit that I missed when I updated the X86 backend to account for the Win64 calling convention on non-Windows. Now we don't use dead non-volatile registers when emitting a Win64 indirect tail call on non-Windows. Should fix PR23710. Test Plan: Added test for the correct behavior based on the case I posted to PR23710. Reviewers: rnk Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10258 llvm-svn: 239111
* [Object, MachO] Don't crash on incomplete MachO segment load commands.Alexey Samsonov2015-06-042-0/+3
| | | | | | | | Report proper error code from MachOObjectFile constructor if we can't parse another segment load command (we already return a proper error if segment load command contents is suspicious). llvm-svn: 239109
* [SDAG switch lowering] Fix switch case -> or merging for 0 and INT_MINBenjamin Kramer2015-06-041-1/+20
| | | | | | | | | | | The big/small ordering here is based on signed values so SmallValue will be INT_MIN and BigValue 0. This shouldn't be a problem but the code assumed that BigValue always had more bits set than SmallValue. We used to just miss the transformation, but a recent refactoring of mine turned this into an assertion failure. llvm-svn: 239105
* Shouldn't be XFAIL'ed.Colin LeMahieu2015-06-041-1/+0
| | | | llvm-svn: 239103
* Revert r239095 incorrect test tree.Colin LeMahieu2015-06-042-7/+1
| | | | llvm-svn: 239102
* [NVPTX] roll forward r239082Jingyue Wu2015-06-046-18/+44
| | | | | | | | | NVPTXISelDAGToDAG translates "addrspacecast to param" to NVPTX::nvvm_ptr_gen_to_param Added an llc test in bug21465. llvm-svn: 239100
* [Hexagon] Adding functionality for duplexing. Duplexing is a way to ↵Colin LeMahieu2015-06-041-0/+7
| | | | | | compress commonly used pairs of instructions in order to reduce code size. The test case duplex.ll normally would be 8 bytes, assign register to 0 and jump to link register. After duplexing this is only 4 bytes. This also tests the HexagonMCShuffler code path which is used to make sure duplexed instructions still follow slot requirements. llvm-svn: 239095
* Revert r239082Jingyue Wu2015-06-046-40/+18
| | | | | | llc crashed for NVPTX backend llvm-svn: 239094
* Erase constant dbgloc on reuse in PHI nodeSergey Dmitrouk2015-06-041-0/+81
| | | | | | | | | | | | | | | | | | | | Basic block selection involves checking successor BBs for PHI nodes that depend on the current BB. In case such BBs are found, the value being selected is a constant and such constant already exists in current BB, it's value is reused. This might lead to wrong locations in some situations, especially if same constant value ends up being materialized twice in two different ways, which discards that sharing and leaves us with wrong debug location in the successor BB. In code this involves the following sequence of calls: SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks -> SelectionDAGBuilder::CopyValueToVirtualRegister -> SelectionDAGBuilder::getNonRegisterValue llvm-svn: 239089
* [GlobalMerge] Take into account minsize on Global users' parents.Ahmed Bougacha2015-06-041-0/+74
| | | | | | | | | | Now that we can look at users, we can trivially do this: when we would have otherwise disabled GlobalMerge (currently -O<3), we can just run it for minsize functions, as it's usually a codesize win. Differential Revision: http://reviews.llvm.org/D10054 llvm-svn: 239087
* MC: Remove obsolete MachO UseAggressiveSymbolFolding.Jim Grosbach2015-06-042-52/+16
| | | | | | | | | | Fix the FIXME and remove this old as(1) compat option. It was useful for bringup of the integrated assembler to diff object files, but now it's just causing more relocations than strictly necessary to be generated. rdar://21201804 llvm-svn: 239084
* [NVPTX] kernel pointer arguments point to the global address spaceJingyue Wu2015-06-046-18/+40
| | | | | | | | | | | | | | | | | | | | | | | | Summary: With this patch, NVPTXLowerKernelArgs converts a kernel pointer argument to a pointer in the global address space. This change, along with NVPTXFavorNonGenericAddrSpaces, allows the NVPTX backend to emit ld.global.* and st.global.* for accessing kernel pointer arguments. Minor changes: 1. refactor: extract function convertToPointerInAddrSpace 2. fix a bug in the test case in bug21465.ll Test Plan: lower-kernel-ptr-arg.ll Reviewers: eliben, meheff, jholewinski Reviewed By: jholewinski Subscribers: wengxt, jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D10154 llvm-svn: 239082
* [Object, MachO] Don't crash on invalid MachO segment load commands.Alexey Samsonov2015-06-041-2/+2
| | | | | | | | | | | | | | | Summary: Properly report the error in segment load commands from MachOObjectFile constructor instead of crashing the program. Adjust the test case accordingly. Test Plan: regression test suite Reviewers: rafael, filcab Subscribers: llvm-commits llvm-svn: 239081
* [Object, MachO] Don't crash on invalid MachO load commands.Alexey Samsonov2015-06-041-2/+2
| | | | | | | | | | | | | | | Summary: Currently all load commands are parsed in MachOObjectFile constructor. If the next load command cannot be parsed, or if command size is too small, properly report it through the error code and fail to construct the object, instead of crashing the program. Test Plan: regression test suite Reviewers: rafael, filcab Subscribers: llvm-commits llvm-svn: 239080
* [Object, MachO] Don't crash on parsing invalid MachO header.Alexey Samsonov2015-06-042-0/+3
| | | | | | | | | | | Summary: Instead, properly report this error from MachOObjectFile constructor. Test Plan: regression test suite Reviewers: rafael Subscribers: llvm-commits llvm-svn: 239078
* Fix buildbot failure on Windows by relaxing test expectations.Alexey Samsonov2015-06-041-1/+2
| | | | llvm-svn: 239074
* [bpf] add big- and host- endian supportAlexei Starovoitov2015-06-0414-18/+109
| | | | | | | | | | | | | | | | | | | Summary: -march=bpf -> host endian -march=bpf_le -> little endian -match=bpf_be -> big endian Test Plan: v1 was tested by IBM s390 guys and appears to be working there. It bit rots too fast here. Reviewers: chandlerc, tstellarAMD Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10177 llvm-svn: 239071
* [DAGCombiner] Fix wrong folding of a build_vector into a blend with zero.Andrea Di Biagio2015-06-041-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Method 'visitBUILD_VECTOR' in the DAGCombiner knows how to combine a build_vector of a bunch of extract_vector_elt nodes and constant zero nodes into a shuffle blend with a zero vector. However, method 'visitBUILD_VECTOR' forgot that a floating point build_vector may contain negative zero as well as positive zero. Example: define <2 x double> @example(<2 x double> %A) { entry: %0 = extractelement <2 x double> %A, i32 0 %1 = insertelement <2 x double> undef, double %0, i32 0 %2 = insertelement <2 x double> %1, double -0.0, i32 1 ret <2 x double> %2 } Before this patch, llc (with -mattr=+sse4.1) wrongly generated movq %xmm0, %xmm0 # xmm0 = xmm0[0],zero So, the sign bit of the negative zero was effectively lost. This patch fixes the problem by adding explicit checks for positive zero. With this patch, llc produces the following code for the example above: movhpd .LCPI0_0(%rip), %xmm0 where .LCPI0_0 referes to a 'double -0'. llvm-svn: 239070
* Make test case more readable: move CHECK-lines next to corresponding RUN-lines.Alexey Samsonov2015-06-041-8/+6
| | | | llvm-svn: 239068
* llvm-objdump: return non-zero exit code for certain cases of invalid inputAlexey Samsonov2015-06-041-0/+5
| | | | | | | | * If the input file is missing; * If the type of input object file can't be recognized; * If the object file can't be parsed correctly. llvm-svn: 239065
* R600/SI: Reimplement isLegalAddressingModeMatt Arsenault2015-06-041-0/+242
| | | | | | | | | | | Now that we sometimes know the address space, this can theoretically do a better job. This needs better test coverage, but this mostly depends on first updating the loop optimizatiosn to provide the address space. llvm-svn: 239053
* R600/SI: Fix some cases for load / store of halfMatt Arsenault2015-06-042-40/+559
| | | | | | | Mostly argument loads were producing broken zextloads from an FP type. llvm-svn: 239049
* Switch lowering: fix assert in buildBitTests (PR23738)Hans Wennborg2015-06-041-0/+15
| | | | | | | | When checking (High - Low + 1).sle(BitWidth), BitWidth would be truncated to the size of the left-hand side. In the case of this PR, the left-hand side was i4, so BitWidth=64 got truncated to 0 and the assert failed. llvm-svn: 239048
* Omit unused section symbols from the symbol table.Rafael Espindola2015-06-0415-144/+50
| | | | | | | | | | | | | | Section symbols exist as an optimization: instead of having multiple relocations point to different symbols, many of them can point to a single section symbol. When that optimization is unused, a section symbol is also unused and adds no extra information to the object file. This saves a bit of space on the object files and makes the output of llvm-objdump -t easier to read and consequently some tests get quite a bit simpler. llvm-svn: 239045
* Move test that depends on x86 to the x86 directory.Rafael Espindola2015-06-041-1/+1
| | | | llvm-svn: 239043
* No need to check the raw relocation bytes if checking the parsed dump.Rafael Espindola2015-06-041-6/+2
| | | | llvm-svn: 239042
* llvm-readobj can parse relocations, no need to check the raw bytes.xRafael Espindola2015-06-041-11/+7
| | | | llvm-svn: 239041
* Disassemble the start of sections even if there is no symbol there.Rafael Espindola2015-06-042-0/+9
| | | | | | | We already handled a section with no symbols, extend that to also handle a section with symbols that don't include the section start. llvm-svn: 239039
* Don't create a MIN/MAX node if the underlying compare has more than one use.James Molloy2015-06-041-0/+11
| | | | | | | | | If the compare in a select pattern has another use then it can't be removed, so we'd just be creating repeated code if we created a min/max node. Spotted by Matt Arsenault! llvm-svn: 239037
* AVX-512: I brought back vector-shuffle-512-v8.ll test.Elena Demikhovsky2015-06-041-0/+1153
| | | | | | I re-generated it after all AVX-512 shuffle optimizations. llvm-svn: 239026
* Test commitIgor Breger2015-06-041-0/+1
| | | | llvm-svn: 239019
* Make the test introduced in r239015 more targeted.David Majnemer2015-06-042-29/+4
| | | | | | | | We don't need to go through LSR to trigger this bug. Instead, hand-craft a tricky GEP and get the constant folder to hack on it when parsing the IR. llvm-svn: 239017
* AVX-512: added all SKX forms of VPERMW/D/Q instructions.Elena Demikhovsky2015-06-042-0/+379
| | | | | | | Added all forms of VPERMPS/PD instrcuctions. Added encoding tests. llvm-svn: 239016
* [ConstantFold] Don't skip the first gep index when folding gepsDavid Majnemer2015-06-041-0/+29
| | | | | | | | | We neglected to check if the first index made the GEP ineligible for 'inbounds'. This fixes PR23753. llvm-svn: 239015
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