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| author | Benjamin Kramer <benny.kra@googlemail.com> | 2015-06-04 22:05:51 +0000 |
|---|---|---|
| committer | Benjamin Kramer <benny.kra@googlemail.com> | 2015-06-04 22:05:51 +0000 |
| commit | ff0fb6936b43d575ca23cf769bf24d9a963e6f19 (patch) | |
| tree | 8e459485d30e34d2f96e62aee9d6d1a4e2073da0 /llvm/test | |
| parent | d772ef3d9f8f54928043bdf4cb1518e82d254542 (diff) | |
| download | bcm5719-llvm-ff0fb6936b43d575ca23cf769bf24d9a963e6f19.tar.gz bcm5719-llvm-ff0fb6936b43d575ca23cf769bf24d9a963e6f19.zip | |
[SDAG switch lowering] Fix switch case -> or merging for 0 and INT_MIN
The big/small ordering here is based on signed values so SmallValue will
be INT_MIN and BigValue 0. This shouldn't be a problem but the code
assumed that BigValue always had more bits set than SmallValue.
We used to just miss the transformation, but a recent refactoring of
mine turned this into an assertion failure.
llvm-svn: 239105
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/X86/switch-or.ll | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/X86/switch-or.ll b/llvm/test/CodeGen/X86/switch-or.ll index 6e6b013d9fa..4642accfff8 100644 --- a/llvm/test/CodeGen/X86/switch-or.ll +++ b/llvm/test/CodeGen/X86/switch-or.ll @@ -1,10 +1,11 @@ ; RUN: llc -march=x86 -asm-verbose=false < %s | FileCheck %s ; Check that merging switch cases that differ in one bit works. +; CHECK-LABEL: test1 ; CHECK: orl $2 ; CHECK-NEXT: cmpl $6 -define void @foo(i32 %variable) nounwind { +define void @test1(i32 %variable) nounwind { entry: switch i32 %variable, label %if.end [ i32 4, label %if.then @@ -19,4 +20,22 @@ if.end: ret void } +; CHECK-LABEL: test2 +; CHECK: orl $-2147483648 +; CHECK-NEXT: cmpl $-2147483648 +define void @test2(i32 %variable) nounwind { +entry: + switch i32 %variable, label %if.end [ + i32 0, label %if.then + i32 -2147483648, label %if.then + ] + +if.then: + %call = tail call i32 (...) @bar() nounwind + ret void + +if.end: + ret void +} + declare i32 @bar(...) nounwind |
