summaryrefslogtreecommitdiffstats
path: root/llvm/test
Commit message (Collapse)AuthorAgeFilesLines
* [SystemZ] Extend memcmp support to all constant lengthsRichard Sandiford2013-08-282-4/+96
| | | | | | This uses the infrastructure added for memcpy and memmove in r189331. llvm-svn: 189458
* [mips] Use ptr_rc to simplify definitions of base+index load/store instructions.Akira Hatanaka2013-08-288-2/+90
| | | | | | Also, fix predicates. llvm-svn: 189432
* Add support for DW_FORM_dataN and DW_FORM_udata to the DIE hashingEric Christopher2013-08-281-2/+2
| | | | | | | algorithm. Update the split dwarf hashing testcase accordingly - this should be the last time that the hash of an empty file changes. llvm-svn: 189427
* Use DW_FORM_sdata for signed constant values and udata on occasionEric Christopher2013-08-274-8/+12
| | | | | | | | | | when we can. Migrate from using blocks when we're adding just a single attribute and floating point values are an unsigned, not signed, bag of bits. Update all test cases accordingly. llvm-svn: 189419
* Move some debug testcases to the debug info directory.Eric Christopher2013-08-2716-0/+0
| | | | llvm-svn: 189418
* DataFlowSanitizer: Implement trampolines for function pointers passed to ↵Peter Collingbourne2013-08-272-5/+17
| | | | | | | | custom functions. Differential Revision: http://llvm-reviews.chandlerc.com/D1503 llvm-svn: 189408
* [ms-inline asm] Support offsets after segment registersDavid Majnemer2013-08-271-0/+6
| | | | | | | | | | | | | | Summary: MASM let's you do stuff like 'MOV FS:20, EAX' and 'MOV EAX, FS:20' Reviewers: craig.topper, rnk Reviewed By: rnk CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1470 llvm-svn: 189407
* Given target assembler parsers a chance to handle variant expressionsJoerg Sonnenberger2013-08-272-0/+7
| | | | | | | first. Use this to turn the PPC modifiers into PPC specific expressions, allowing them to work on constants. llvm-svn: 189400
* [ARMv8] Add MC support for the new load/store acquire/release instructions.Joey Gouly2013-08-274-0/+131
| | | | llvm-svn: 189388
* AVX-512: added conversion instructions.Elena Demikhovsky2013-08-271-0/+186
| | | | llvm-svn: 189349
* DAGCombiner: make sure or/shl/srl really has zero high bits before forming bswapTim Northover2013-08-271-6/+101
| | | | | | | | We want to convert code like (or (srl N, 8), (shl N, 8)) into (srl (bswap N), const), but this is only valid if the bits above 16 on the source pattern are 0, the checks we were doing on this were slightly wrong before. llvm-svn: 189348
* [ARMv8] Add some negative tests for the recent VFP/NEON instructions.Joey Gouly2013-08-272-3/+108
| | | | | | Fix two issues I found while writing these tests. llvm-svn: 189341
* ARM: add natural patterns for vaddhl and vsubhl.Tim Northover2013-08-272-0/+54
| | | | | | | | These instructions aren't particularly complicated and it's well worth having patterns for some reasonably useful LLVM IR that will match them. Soon we should be able to switch Clang over to producing this natural version. llvm-svn: 189335
* R600/SI: Enable local-memory-two-objects lit testMichel Danzer2013-08-271-12/+17
| | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 189334
* [mips][msa] Added tests for and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v ↵Daniel Sanders2013-08-271-43/+523
| | | | | | | | | | | | when non-byte vectors are used. Note that all of these tests use ld.b and st.b for the loads and stores regardless of the data size. This is because the definition of bitcast is equivalent to a store/load sequence and DAG combiner accordingly folds bitcasts to/from v16i8 into the load/store nodes to product load/store nodes with type v16i8. llvm-svn: 189333
* [mips][msa] Added spill/reload supportDaniel Sanders2013-08-271-0/+597
| | | | llvm-svn: 189332
* [SystemZ] Extend memcpy and memset support to all constant lengthsRichard Sandiford2013-08-275-29/+224
| | | | | | | | | | | | | | Lengths up to a certain threshold (currently 6 * 256) use a series of MVCs. Lengths above that threshold use a loop to handle X*256 bytes followed by a single MVC to handle the excess (if any). This loop will also be needed in future when support for variable lengths is added. Because the same tablegen classes are used to define MVC and CLC, the patch also has the side-effect of defining a pseudo loop instruction for CLC. That instruction isn't used yet (and wouldn't be handled correctly if it were). I'm planning to use it soon though. llvm-svn: 189331
* [mips][msa] Added bitconverts for vector types for big and little-endianDaniel Sanders2013-08-271-0/+1208
| | | | llvm-svn: 189330
* AVX-512: Added FMA instructions.Elena Demikhovsky2013-08-271-0/+83
| | | | llvm-svn: 189326
* Fix wrong code offset for unwind code SET_FPREG.Kai Nacke2013-08-272-3/+1
| | | | | | | | | | | | The code offset for unwind code SET_FPREG is wrong because it is set to constant 0. The fix is to do the same as for the other unwind codes: emit a label and later the absolute difference between the label and the begin of the prologue. Also enables the failing test case MC/COFF/seh.s Reviewed by Jim Grosbach, Charles Davis and Nico Rieck. llvm-svn: 189309
* Add derived from source.Eric Christopher2013-08-271-0/+5
| | | | llvm-svn: 189301
* Add a testcase to ensure that the pubnames section uses an offsetEric Christopher2013-08-271-0/+32
| | | | | | off of the debug_info section even when split dwarf is enabled. llvm-svn: 189300
* Fix lint assert on integer vector divisionMatt Arsenault2013-08-262-0/+79
| | | | llvm-svn: 189290
* Treat the pubtypes section similarly to the pubnames section and emitEric Christopher2013-08-261-1/+1
| | | | | | | | | it by default under linux or when we're trying to keep compatibility with old gdb versions. Fix testcase for option name change. llvm-svn: 189289
* Fix inserting instructions before last in bundle.Matt Arsenault2013-08-261-1/+1
| | | | | | | | | | | The builder inserts from before the insert point, not after, so this would insert before the last instruction in the bundle instead of after it. I'm not sure if this can actually be a problem with any of the current insertions. llvm-svn: 189285
* Debug Info: add an identifier field to DICompositeType.Manman Ren2013-08-26179-472/+472
| | | | | | | | | | | | | | | | | | DICompositeType will have an identifier field at position 14. For now, the field is set to null in DIBuilder. For DICompositeTypes where the template argument field (the 13th field) was optional, modify DIBuilder to make sure the template argument field is set. Now DICompositeType has 15 fields. Update DIBuilder to use NULL instead of "i32 0" for null value of a MDNode. Update verifier to check that DICompositeType has 15 fields and the last field is null or a MDString. Update testing cases to include an extra field for DICompositeType. The identifier field will be used by type uniquing so a front end can genearte a DICompositeType with a unique identifer. llvm-svn: 189282
* LoopVectorize: Implement partial loop unrolling when vectorization is not ↵Nadav Rotem2013-08-261-0/+39
| | | | | | | | | | | | | | | | profitable. This patch enables unrolling of loops when vectorization is legal but not profitable. We add a new class InnerLoopUnroller, that extends InnerLoopVectorizer and replaces some of the vector-specific logic with scalars. This patch does not introduce any runtime regressions and improves the following workloads: SingleSource/Benchmarks/Shootout/matrix -22.64% SingleSource/Benchmarks/Shootout-C++/matrix -13.06% External/SPEC/CINT2006/464_h264ref/464_h264ref -3.99% SingleSource/Benchmarks/Adobe-C++/simple_types_constant_folding -1.95% llvm-svn: 189281
* ARM: Enable machine verifier for a few more tests.Jim Grosbach2013-08-262-3/+3
| | | | | | | | | Now that fast-isel is in better shape, we can enable the machine verifier for these tests, too. rdar://12594152 llvm-svn: 189275
* ARM: Constrain regclass for TSTri instruction.Jim Grosbach2013-08-261-1/+1
| | | | | | | | | Get the register class right for the TST instruction. This keeps the machine verifier happy, enabling us to turn it on for another test. rdar://12594152 llvm-svn: 189274
* ARM: FastISel verifier error cleanup.Jim Grosbach2013-08-261-1/+1
| | | | | | | | | Constant pool and global value reference instructions need more restricted register classes than plain GPR. rdar://12594152 llvm-svn: 189270
* [PowerPC] More fast-isel chunks (returns and integer extends)Bill Schmidt2013-08-262-0/+217
| | | | | | | | | | | | | | | | | Incremental improvement to fast-isel for PPC64. This allows us to select on ret, sext, and zext. Filling in sext/zext improves some of the existing logic in handling compare-immediates that needed extends. A simplified return convention for fast-isel is also added to the PPC64 calling conventions. All call/return processing for DAG selection is handled with custom code, so there isn't an existing CC to rely on here. The include of PPCGenCallingConv.inc causes compiler warnings due to the 32-bit calling conventions that are not used, so the dummy function "usePPC32CCs()" is added here to silence those. Test cases for the return and extend logic are added. llvm-svn: 189266
* Forgot to add slp threshold to testMatt Arsenault2013-08-261-1/+2
| | | | llvm-svn: 189248
* Vectorize starting from insertelements building a vectorMatt Arsenault2013-08-261-0/+196
| | | | llvm-svn: 189233
* SelectionDAG: Remove unnecessary uses of TargetLowering::getPointerTy()Tom Stellard2013-08-261-0/+140
| | | | | | | | | | | | If we have a binary operation like ISD:ADD, we can set the result type equal to the result type of one of its operands rather than using TargetLowering::getPointerTy(). Also, any use of DAG.getIntPtrConstant(C) as an operand for a binary operation can be replaced with: DAG.getConstant(C, OtherOperand.getValueType()); llvm-svn: 189227
* R600: Add support for vector local memory loadsTom Stellard2013-08-261-0/+14
| | | | llvm-svn: 189226
* R600: Add support for i8 and i16 local memory loadsTom Stellard2013-08-261-0/+78
| | | | llvm-svn: 189225
* SelectionDAG: Use correct pointer size when splitting vector storesTom Stellard2013-08-261-0/+15
| | | | llvm-svn: 189224
* R600: Add support for i8 and i16 local memory storesTom Stellard2013-08-261-0/+18
| | | | llvm-svn: 189223
* R600: Add support for v4i32 and v2i32 local storesTom Stellard2013-08-261-0/+52
| | | | llvm-svn: 189222
* SelectionDAG: Use correct pointer size when lowering function arguments v2Tom Stellard2013-08-261-0/+42
| | | | | | | | | | | | | | | | This adds minimal support to the SelectionDAG for handling address spaces with different pointer sizes. The SelectionDAG should now correctly lower pointer function arguments to the correct size as well as generate the correct code when lowering getelementptr. This patch also updates the R600 DataLayout to use 32-bit pointers for the local address space. v2: - Add more helper functions to TargetLoweringBase - Use CHECK-LABEL for tests llvm-svn: 189221
* AVX-512: Added shuffle instructions - Elena Demikhovsky2013-08-261-0/+62
| | | | | | | VPSHUFD, VPERMILPS, VMOVDDUP, VMOVLHPS, VMOVHLPS, VSHUFPS, VALIGN single and double forms. llvm-svn: 189215
* This patch implements trap instructions for mips. The test cases are added.Vladimir Medic2013-08-261-2/+58
| | | | llvm-svn: 189213
* [PowerPC] Add fast-isel branch and compare selection.Bill Schmidt2013-08-252-0/+58
| | | | | | | | | | | First chunk of actual fast-isel selection code. This handles direct and indirect branches, as well as feeding compares for direct branches. PPCFastISel::PPCEmitIntExt() is just roughed in and will be expanded in a future patch. This also corrects a problem with selection for constant pool entries in JIT mode or with small code model. llvm-svn: 189202
* First round of fixes for the x86 fixes for the x86 move accumulator from/to ↵Craig Topper2013-08-253-4/+70
| | | | | | | | | | | | | | memory offset instructions. -Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted. -x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size. -Intel syntax printing prints the ptr size and places brackets around the address immediate. Known remaining issues with these instructions: -Segment override prefix is not supported. PR16962 and PR16961. -Immediate size should be changed by address size prefix. llvm-svn: 189201
* [Sparc] Add long double (f128) instructions to sparc backend. Venkatraman Govindaraju2013-08-251-0/+27
| | | | llvm-svn: 189198
* [Sparc] Added V9's extra floating point registers and their aliases.Venkatraman Govindaraju2013-08-251-0/+23
| | | | llvm-svn: 189195
* AVX-512: added UNPACK instructions and tests for all-zero/all-ones vectorsElena Demikhovsky2013-08-252-11/+62
| | | | llvm-svn: 189189
* Start to add the LLVM builtins to the mips16 exclusion lists for fp.Reed Kotler2013-08-251-0/+28
| | | | | | | | | | | | | I need to add the rest of these to the list or else to delay putting out the actual stub until later in code generation when I know if the external function ever got emitted Resubmit this patch. The target triple needs to be added to the test so that clang does not tell the backend the wrong target when the host is BSD. There is a clang bug in here somewhere that I need to track down. At Mips this has been filed internally as a bug. llvm-svn: 189186
* Revert 189161Shuxin Yang2013-08-241-28/+0
| | | | llvm-svn: 189176
* Start to add the builtind to the mips16 exclusion lists for fp.Reed Kotler2013-08-241-0/+28
| | | | | | | | I need to add the rest of these to the list or else to delay putting out the actual stub until later in code generation when I know if the external function ever got emitted. llvm-svn: 189161
OpenPOWER on IntegriCloud