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* [mips] [IAS] Merge the micromips-expressions.s test into expr1.s. NFC.Toma Tabacu2015-05-132-49/+32
| | | | | | | | | | | | | | Summary: Also did some minor reformatting in the resulting test. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9702 llvm-svn: 237242
* [DebugInfo] Debug locations for constant SD nodesSergey Dmitrouk2015-05-136-6/+150
| | | | | | | | | | | | | | | | | | | | | Several updates for [DebugInfo] Add debug locations to constant SD nodes (r235989). Includes: * re-enabling the change (disabled recently); * missing change for FP constants; * resetting debug location of constant node if it's used more than at one place to prevent emission of wrong locations in case of coalesced constants; * a couple of additional tests. Now all look ups in CSEMap are wrapped by additional method. Comment in D9084 suggests that debug locations aren't useful for "target constants", so there might be one more change related to this API (namely, dropping debug locations for getTarget*Constant methods). Differential Revision: http://reviews.llvm.org/D9604 llvm-svn: 237237
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-05-131-1/+1
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first two times this was committed (r229831, r233055), it caused several buildbot failures. At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed. llvm-svn: 237234
* AVX-512: fixed a bug in encoding of VPSRAQ instrcution,Elena Demikhovsky2015-05-131-1/+914
| | | | | | added a bunch of encoding tests. llvm-svn: 237232
* [SLSR] handles non-canonicalized Mul candidatesJingyue Wu2015-05-131-0/+21
| | | | | | | | such as (2 + B) * S. Tested by @non_canonicalized in slsr-mul.ll llvm-svn: 237216
* [Statepoints] Support for "patchable" statepoints.Sanjoy Das2015-05-1242-248/+315
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change adds two new parameters to the statepoint intrinsic, `i64 id` and `i32 num_patch_bytes`. `id` gets propagated to the ID field in the generated StackMap section. If the `num_patch_bytes` is non-zero then the statepoint is lowered to `num_patch_bytes` bytes of nops instead of a call (the spill and reload code remains unchanged). A non-zero `num_patch_bytes` is useful in situations where a language runtime requires complete control over how a call is lowered. This change brings statepoints one step closer to patchpoints. With some additional work (that is not part of this patch) it should be possible to get rid of `TargetOpcode::STATEPOINT` altogether. PlaceSafepoints generates `statepoint` wrappers with `id` set to `0xABCDEF00` (the old default value for the ID reported in the stackmap) and `num_patch_bytes` set to `0`. This can be made more sophisticated later. Reviewers: reames, pgavlin, swaroop.sridhar, AndyAyers Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9546 llvm-svn: 237214
* CodeGen: ignore DEBUG_VALUE nodes in KILL taggingSaleem Abdulrasool2015-05-121-0/+88
| | | | | | | DEBUG_VALUE nodes do not take part in code generation. Ignore them when performing KILL updates. Addresses PR23486. llvm-svn: 237211
* Revert r237175: [X86] Always return the sret parameter in eax/rax ...Chandler Carruth2015-05-122-41/+19
| | | | | | | This commit broke an x86 test and the bots have been broken for well over an hour now so I'm just reverting. llvm-svn: 237210
* CVP: Improve handling of Selects used as incoming PHI valuesBjorn Steinbrink2015-05-121-0/+53
| | | | | | | | | | | | | | Summary: If the branch that leads to the PHI node and the Select instruction depend on correlated conditions, we might be able to directly use the corresponding value from the Select instruction as the incoming value for the PHI node, allowing later removal of the select instruction. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9051 llvm-svn: 237201
* [RewriteStatepointsForGC] Extend base pointer to handle more cases w/vectorsPhilip Reames2015-05-121-0/+25
| | | | | | | | | | When relocating a pointer, we need to determine a base pointer for the derived pointer being relocated. We have limited support for handling a pointer extracted from a vector; the current code only handled the case where the entire vector was known to contain base pointers. This patch extends the reasoning to handle chains of insertelements where the indices are constants. This case turns out to be fairly common in vectorized code. We can now handle vectors which contains mixtures of base and derived pointers provided the insertelements use constant indices. Note that this doesn't solve the general problem. To handle variable indexed insertelements, we'd need to scalarize and introduce conditional branching based on the index. Alternatively, we could eagerly scalarize, but the code structure doesn't currently make either fix easy. The patch also doesn't handle shufflevector or other vector manipulation for much the same reasons. I plan to defer this work until I have a motivating test case. Differential Revision: http://reviews.llvm.org/D9676 llvm-svn: 237200
* MergeFunctions: Two different sized allocas are *not* the sameArnold Schwaighofer2015-05-121-0/+33
| | | | llvm-svn: 237193
* [X86] Always return the sret parameter in eax/rax, even on 32-bitReid Kleckner2015-05-122-19/+41
| | | | | | | | | | | | | | | | | | | Summary: This rule was always in the old SysV i386 ABI docs and the new ones that H.J. Lu has put together, but we never noticed: EAX scratch register; also used to return integer and pointer values from functions; also stores the address of a returned struct or union Fixes PR23491. Reviewers: majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9715 llvm-svn: 237175
* [PlaceSafepoints] Remove dependence on LoopSimplifyPhilip Reames2015-05-121-4/+4
| | | | | | | | As a step towards getting rid of internal pass manager hack entirely, remove the need for loop simplify to run in the inner pass manager. The new code does produce slightly different loop structures, so this isn't technically NFC. Differential Revision: http://reviews.llvm.org/D9585 llvm-svn: 237172
* [PATCH] [HEXAGON] Add a test program to verify calling conventionSundeep Kushwaha2015-05-121-0/+13
| | | | | | | | for large struct return by value. Differential Revision: http://reviews.llvm.org/D9709 llvm-svn: 237170
* [Statepoints] Split the calling convention and statepoint flags operand to ↵Pat Gavlin2015-05-122-4/+19
| | | | | | | | STATEPOINT into two separate operands. Differential Revision: http://reviews.llvm.org/D9623 llvm-svn: 237166
* [mips][microMIPSr6] Implement SELEQZ and SELNEZ instructionsJozef Kolek2015-05-122-0/+6
| | | | | | | | This patch implements SELEQZ and SELNEZ instructions using mapping. Differential Revision: http://reviews.llvm.org/D8497 llvm-svn: 237158
* Reimplement heuristic for estimating complete-unroll optimization effects.Michael Zolotukhin2015-05-122-2/+36
| | | | | | | | | | | | | | | | | | | | Summary: This patch reimplements heuristic that tries to estimate optimization beneftis from complete loop unrolling. In this patch I kept the minimal changes - e.g. I removed code handling branches and folding compares. That's a promising area, but now there are too many questions to discuss before we can enable it. Test Plan: Tests are included in the patch. Reviewers: hfinkel, chandlerc Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8816 llvm-svn: 237156
* [Mips] Return false for isFPCloseToIncomingSP()Petar Jovanovic2015-05-121-0/+32
| | | | | | | | | | | | | On Mips, frame pointer points to the same side of the frame as the stack pointer. This function is used to decide where to put register scavenging spill slot. So far, it was put on the wrong side of the frame, and thus it was too far away from $fp when frame was larger than 2^15 bytes. Patch by Vladimir Radosavljevic. http://reviews.llvm.org/D8895 llvm-svn: 237153
* R600/SI: add pass to mark CF live ranges as non-spillableTom Stellard2015-05-121-0/+501
| | | | | | | | | | | | | | | | | | | | | | Spilling can insert instructions almost anywhere, and this can mess up control flow lowering in a multitude of ways, due to instruction reordering. Let's sort this out the easy way: never spill registers involved with control flow, i.e. saved EXEC masks. Unfortunately, this does not work at all with optimizations disabled, as the register allocator ignores spill weights. This should be addressed in a future commit. The test was reduced from the "stacks" shader of [1]. Some issues trigger the machine verifier while another one is checked manually. [1] http://madebyevan.com/webgl-path-tracing/ v2: only insert pass with optimizations enabled, merge test runs. Patch by: Grigori Goronzy llvm-svn: 237152
* Changed renaming of local symbols by inserting a dot vefore the numeric suffix.Sunil Srivastava2015-05-1228-120/+120
| | | | | | | One code change and several test changes to match that details in http://reviews.llvm.org/D9481 llvm-svn: 237150
* [DWARF] Add CIE header fields address_size and segment_size when generating ↵Keith Walker2015-05-123-6/+30
| | | | | | | | | | | | | dwarf-4 The DWARF-4 specification added 2 new fields in the CIE header called address_size and segment_size. Create these 2 new fields when generating dwarf-4 CIE entries, print out the new fields when dumping the CIE and update tests Differential Revision: http://reviews.llvm.org/D9558 llvm-svn: 237145
* R600/SI: Remove M0Reg register classTom Stellard2015-05-121-1/+1
| | | | | | It is no longer used. llvm-svn: 237142
* R600/SI: Remove explicit m0 operand from DS instructionsTom Stellard2015-05-122-2/+2
| | | | | | | Instead add m0 as an implicit operand. This helps avoid spills of the m0 register in some cases. llvm-svn: 237141
* R600/SI: Make sendmsg test more strictTom Stellard2015-05-121-0/+2
| | | | | | We want to make sure that the m0 copies are being cse'd. llvm-svn: 237134
* AVX-512, X86: Added lowering for shift operations for SKX.Elena Demikhovsky2015-05-121-0/+29
| | | | | | | | The other changes in the LowerShift() are not functional, just to make the code more convenient. So, the functional changes for SKX only. llvm-svn: 237129
* [ARM] Use AEABI aligned function variantsJohn Brawn2015-05-121-31/+82
| | | | | | | | | | | AEABI defines aligned variants of memcpy etc. that can be faster than the default version due to not having to do alignment checks. When emitting target code for these functions make use of these aligned variants if possible. Also convert memset to memclr if possible. Differential Revision: http://reviews.llvm.org/D8060 llvm-svn: 237127
* Reverse ordering of base and derived pointer during safepoint lowering.Igor Laevsky2015-05-122-21/+136
| | | | | | | | According to the documentation in StackMap section for the safepoint we should have: "The first Location in each pair describes the base pointer for the object. The second is the derived pointer actually being relocated." But before this change we emitted them in reverse order - derived pointer first, base pointer second. llvm-svn: 237126
* [mips][FastISel] Handle calls with non legal types i8 and i16.Vasileios Kalintiris2015-05-121-0/+184
| | | | | | | | | | | | | | | | | | Summary: Allow calls with non legal integer types based on i8 and i16 to be processed by mips fast-isel. Based on a patch by Reed Kotler. Test Plan: "Make check" test forthcoming. Test-suite passes at O0/O2 and with mips32 r1/r2 Reviewers: rkotler, dsanders Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D6770 llvm-svn: 237121
* [mips][FastISel] Simplify callabi.ll by using multiple check prefixes.Vasileios Kalintiris2015-05-121-397/+274
| | | | | | | | | | Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9635 llvm-svn: 237119
* [mips][FastISel] Allow computation of addresses from constant expressions.Vasileios Kalintiris2015-05-121-0/+18
| | | | | | | | | | | | | | | | | | | Summary: Try to compute addresses when the offset from a memory location is a constant expression. Based on a patch by Reed Kotler. Test Plan: Passes test-suite for -O0/O2 and mips 32 r1/r2 Reviewers: rkotler, dsanders Subscribers: llvm-commits, aemerson, rfuhler Differential Revision: http://reviews.llvm.org/D6767 llvm-svn: 237117
* AVX-512: asm parser errors checkElena Demikhovsky2015-05-121-0/+6
| | | | | | | I reverted the error check that was removed in 236416. I put the it in a separate file. llvm-svn: 237107
* AVX-512: select operation for i1 vectorsElena Demikhovsky2015-05-121-0/+75
| | | | | | | | like: select i1 %cond, <16 x i1> %a, <16 x i1> %b. I added pseudo-CMOV patterns to resolve the "select". Added tests for KNL and SKX. llvm-svn: 237106
* [X86] DAGCombine should not assume arbitrary vector types are simpleMichael Kuperstein2015-05-121-0/+11
| | | | | | | | | The X86-specific DAGCombine for stores should not assume vector types are always simple. This fixes PR23476. Differential Revision: http://reviews.llvm.org/D9659 llvm-svn: 237097
* Migrate existing backends that care about software floating pointEric Christopher2015-05-125-10/+14
| | | | | | | | | | | | | | | | | | | | to use the information in the module rather than TargetOptions. We've had and clang has used the use-soft-float attribute for some time now so have the backends set a subtarget feature based on a particular function now that subtargets are created based on functions and function attributes. For the one middle end soft float check go ahead and create an overloadable TargetLowering::useSoftFloat function that just checks the TargetSubtargetInfo in all cases. Also remove the command line option that hard codes whether or not soft-float is set by using the attribute for all of the target specific test cases - for the generic just go ahead and add the attribute in the one case that showed up. llvm-svn: 237079
* [MemCpyOpt] Look at any dependency -not just source- for memset+memcpy.Ahmed Bougacha2015-05-111-0/+18
| | | | | | | | | | This fixes another miscompile introduced by r235232: when there was a dependency on the memcpy destination other than the memset, we would ignore it, because we only looked at the source dependency. It was a mistake to use SrcDepInfo. Instead, just use DepInfo. llvm-svn: 237066
* [WinEH] Handle nested landing pads that return directly to the parent function.Andrew Kaylor2015-05-115-5/+219
| | | | | | Differential Revision: http://reviews.llvm.org/D9684 llvm-svn: 237063
* [WinEH] Update exception numbering to give handlers their own base state.Andrew Kaylor2015-05-114-3/+300
| | | | | | Differential Revision: http://reviews.llvm.org/D9512 llvm-svn: 237014
* [RewriteStatepointsForGC] Fix a bug on creating gc_relocate for pointer to ↵Sanjoy Das2015-05-118-28/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | vector of pointers Summary: In RewriteStatepointsForGC pass, we create a gc_relocate intrinsic for each relocated pointer, and the gc_relocate has the same type with the pointer. During the creation of gc_relocate intrinsic, llvm requires to mangle its type. However, llvm does not support mangling of all possible types. RewriteStatepointsForGC will hit an assertion failure when it tries to create a gc_relocate for pointer to vector of pointers because mangling for vector of pointers is not supported. This patch changes the way RewriteStatepointsForGC pass creates gc_relocate. For each relocated pointer, we erase the type of pointers and create an unified gc_relocate of type i8 addrspace(1)*. Then a bitcast is inserted to convert the gc_relocate to the correct type. In this way, gc_relocate does not need to deal with different types of pointers and the unsupported type mangling is no longer a problem. This change would also ease further merge when LLVM erases types of pointers and introduces an unified pointer type. Some minor changes are also introduced to gc_relocate related part in InstCombineCalls, CodeGenPrepare, and Verifier accordingly. Patch by Chen Li! Reviewers: reames, AndyAyers, sanjoy Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9592 llvm-svn: 237009
* [X86] Updates to X86 backend for f16 promotionPirama Arumuga Nainar2015-05-111-7/+201
| | | | | | | | | | | | | | | | | | | | | | | Summary: r235215 adds support for f16 to be considered as a load/store type and promote f16 operations to f32. This patch has miscellaneous fixes for the X86 backend so all f16 operations are handled: 1. Set loadextaction for f16 vectors to expand. 2. Handle FP_EXTEND in a switch statement when handling v2f32 3. Do not fold (FP_TO_SINT (load f16)) into FP_TO_INT*_IN_MEM or (store (SINT_TO_FP )) to a FILD. Tests included. Reviewers: ab, srhines, delena Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9092 llvm-svn: 237004
* [Testsuite] Renumber metadata in ScopedNoAliasAA test to match CHECK linesAdam Nemet2015-05-111-13/+11
| | | | | | | | | | | | | | | | | Summary: Now it's much easier to follow what's happening in this test. Also removed some unused metadata entries. Reviewers: hfinkel Reviewed By: hfinkel Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9601 llvm-svn: 236981
* AVX-512: Changed CC parameter in "cmp" intrinsicElena Demikhovsky2015-05-114-408/+408
| | | | | | | | from i8 to i32 according to the Intel Spec by Igor Breger (igor.breger@intel.com) llvm-svn: 236979
* [InstCombine/PowerPC] Fix single-precision QPX load/store replacementHal Finkel2015-05-111-0/+3
| | | | | | | | | | The QPX single-precision load/store intrinsics have implied truncation/extension from/to the declared value type of <4 x double> to the memory type of <4 x float>. When we can prove the alignment of the pointer argument, and thus replace the intrinsic with a regular load or store, we need to load or store the correct data type (<4 x float>) instead of (<4 x double>). llvm-svn: 236973
* AVX-512: Added SKX instructions and intrinsics:Elena Demikhovsky2015-05-114-30/+1218
| | | | | | | | {add/sub/mul/div/} x {ps/pd} x {128/256} 2. max/min with sae By Asaf Badouh (asaf.badouh@intel.com) llvm-svn: 236971
* Make buildbots happyDavid Majnemer2015-05-111-1/+1
| | | | llvm-svn: 236970
* [InstCombine] Canonicalize single element array storeDavid Majnemer2015-05-111-0/+20
| | | | | | | | Use the element type instead of the aggregate type. Differential Revision: http://reviews.llvm.org/D9591 llvm-svn: 236969
* [InstCombine] Canonicalize single element array loadDavid Majnemer2015-05-111-0/+25
| | | | | | | | Use the element type instead of the aggregate type. Differential Revision: http://reviews.llvm.org/D9596 llvm-svn: 236968
* AVX-512: fixed UINT_TO_FP operation for 512-bit types.Elena Demikhovsky2015-05-101-0/+17
| | | | llvm-svn: 236955
* AVX-512: fixed a bug in i1 vectors loweringElena Demikhovsky2015-05-101-1/+50
| | | | llvm-svn: 236947
* llvm/test/CodeGen/AArch64/tailcall_misched_graph.ll: s/REQUIRE/REQUIRES/NAKAMURA Takumi2015-05-091-1/+1
| | | | llvm-svn: 236928
* Fix MergeConsecutiveStore for non-byte-sized memory accesses.James Y Knight2015-05-091-0/+15
| | | | | | | | | | | | | | | | | | | The bug showed up as a compile-time assertion failure: Assertion `NumBits >= MIN_INT_BITS && "bitwidth too small"' failed when building msan tests on x86-64. Prior to r236850, this bug was masked due to a bogus alignment check, which also accidentally rejected non-byte-sized accesses. Afterwards, an invalid ElementSizeBytes == 0 got further into the function, and triggered the assertion failure. It would probably be a good idea to allow it to handle merging stores of unusual widths as well, but for now, to un-break it, I'm just making the minimal fix. Differential Revision: http://reviews.llvm.org/D9626 llvm-svn: 236927
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