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| author | Tom Stellard <thomas.stellard@amd.com> | 2015-05-12 15:00:49 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2015-05-12 15:00:49 +0000 |
| commit | 381a94a7643afdc9025e24219c9700e29adad68f (patch) | |
| tree | 1ba7c8f16d3b38b8a784ff024463c06d1f6cc6c6 /llvm/test | |
| parent | 2a9d94757f51ad304cff29d12a841618caa78d7d (diff) | |
| download | bcm5719-llvm-381a94a7643afdc9025e24219c9700e29adad68f.tar.gz bcm5719-llvm-381a94a7643afdc9025e24219c9700e29adad68f.zip | |
R600/SI: Remove explicit m0 operand from DS instructions
Instead add m0 as an implicit operand. This helps avoid spills
of the m0 register in some cases.
llvm-svn: 237141
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/R600/ds_read2st64.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/shl_add_ptr.ll | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/R600/ds_read2st64.ll b/llvm/test/CodeGen/R600/ds_read2st64.ll index 54b3b45636d..b72e3ef861d 100644 --- a/llvm/test/CodeGen/R600/ds_read2st64.ll +++ b/llvm/test/CodeGen/R600/ds_read2st64.ll @@ -65,8 +65,8 @@ define void @simple_read2st64_f32_max_offset(float addrspace(1)* %out, float add ; SI-LABEL: @simple_read2st64_f32_over_max_offset ; SI-NOT: ds_read2st64_b32 -; SI: v_add_i32_e32 [[BIGADD:v[0-9]+]], 0x10000, {{v[0-9]+}} ; SI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:256 +; SI: v_add_i32_e32 [[BIGADD:v[0-9]+]], 0x10000, {{v[0-9]+}} ; SI: ds_read_b32 {{v[0-9]+}}, [[BIGADD]] ; SI: s_endpgm define void @simple_read2st64_f32_over_max_offset(float addrspace(1)* %out, float addrspace(3)* %lds) #0 { diff --git a/llvm/test/CodeGen/R600/shl_add_ptr.ll b/llvm/test/CodeGen/R600/shl_add_ptr.ll index 066dafb6e8c..6671e909cd1 100644 --- a/llvm/test/CodeGen/R600/shl_add_ptr.ll +++ b/llvm/test/CodeGen/R600/shl_add_ptr.ll @@ -69,8 +69,8 @@ define void @load_shl_base_lds_max_offset(i8 addrspace(1)* %out, i8 addrspace(3) ; pointer can be used with an offset into the second one. ; SI-LABEL: {{^}}load_shl_base_lds_2: +; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} ; SI: s_mov_b32 m0, -1 -; SI-NEXT: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} ; SI-NEXT: ds_read2st64_b32 {{v\[[0-9]+:[0-9]+\]}}, [[PTR]] offset0:1 offset1:9 ; SI: s_endpgm define void @load_shl_base_lds_2(float addrspace(1)* %out) #0 { |
