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* Fixed test name. NFCI.Simon Pilgrim2017-06-201-7/+7
| | | | llvm-svn: 305787
* [GlobalISel][X86] Get correct RegClass for given RegBank.Igor Breger2017-06-201-6/+18
| | | | | | | | | | | | | | | | | | | Summary: In some cases RegClass depends on target feature. Hight (16-31) vector registers exist only if AVX512f available. Split from https://reviews.llvm.org/D33665 Reviewers: qcolombet, t.p.northover, zvi, guyblank Reviewed By: t.p.northover, guyblank Subscribers: guyblank, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D33952 Conflicts: test/CodeGen/X86/GlobalISel/select-memop-scalar.mir llvm-svn: 305784
* [GlobalISel] combine not symmetric merge/unmerge nodes.Igor Breger2017-06-201-6/+6
| | | | | | | | | | | | | | | | Summary: In some cases legalization ends up with not symmetric merge/unmerge nodes. Transform it to merge/unmerge nodes. Reviewers: t.p.northover, qcolombet, zvi Reviewed By: t.p.northover Subscribers: rovka, kristof.beyls, guyblank, llvm-commits Differential Revision: https://reviews.llvm.org/D33626 llvm-svn: 305783
* [GlobalISel][X86] add legalizer mir tests. NFCIgor Breger2017-06-202-73/+205
| | | | llvm-svn: 305781
* [ARM] Support constant pools in data when generating execute-only code.Alexandros Lamprineas2017-06-201-0/+50
| | | | | | | | | | | | | | | | | | Resubmission of r305387, which was reverted at r305390. The Address Sanitizer caught a stack-use-after-scope of a Twine variable. This is now fixed by passing the Twine directly as a function parameter. The ARM backend asserts against constant pool lowering when it generates execute-only code in order to prevent the generation of constant pools in the text section. It appears that target independent optimizations might generate DAG nodes that represent constant pools. By lowering such nodes as global addresses we don't violate the semantics of execute-only code and also it is guaranteed that execute-only behaves correct with the position-independent addressing modes that support execute-only code. Differential Revision: https://reviews.llvm.org/D33773 llvm-svn: 305776
* [WebAssembly] Add support for weak symbols in the binary formatSam Clegg2017-06-203-4/+96
| | | | | | | | | | | This also introduces the updated format for the "linking" section which can represent extra symbol information. See: https://github.com/WebAssembly/tool-conventions/pull/10 Differential Revision: https://reviews.llvm.org/D34019 llvm-svn: 305769
* AMDGPU: Fix scratch wave offset relative FI expansionMatt Arsenault2017-06-191-7/+47
| | | | | | | | The offset may not be an inline immediate, so this needs to be materialized into a register. The post-RA run of SIShrinkInstructions is able to fold it later if it can. llvm-svn: 305761
* [AMDGPU] Add infer address spaces pass before SROAStanislav Mekhanoshin2017-06-191-0/+10
| | | | | | | | | It adds it for the target after inlining but before SROA where we can get most out of it. Differential Revision: https://reviews.llvm.org/D34366 llvm-svn: 305759
* Fix machine instruction in test caseSanjoy Das2017-06-191-3/+3
| | | | | | | | | | The AMD64rm instruction used in the test case was incorrect. Since the first input register to AND64rm is tied to output register, they must be the same. Thanks for Jesper Antonsson for pointing this out! llvm-svn: 305756
* Fix a FIXME in llvm-objdump for the -exports-trie option that was not addingKevin Enderby2017-06-191-0/+10
| | | | | | | | | | in the base address. Without this Mach-O files, like 64-bit executables, don’t have the correct addresses printed for their exports. As the default is to link at address 0x100000000 not zero. llvm-svn: 305744
* [PATCH] [PGO] Fixed cast operation in ↵Ana Pazos2017-06-191-0/+14
| | | | | | | | | | | | | | emIntrinsicVisitor::instrumentOneMemIntrinsic. Reviewers: xur, efriedma, davidxl Reviewed By: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34293 llvm-svn: 305737
* Revert r305382, it caused PR33513.Nico Weber2017-06-191-20/+20
| | | | llvm-svn: 305735
* [CGP, PowerPC] try to constant fold before creating loads for memcmp expansionSanjay Patel2017-06-191-25/+8
| | | | | | | | | | | | | | | This is the last step needed to avoid regressions for x86 before we flip the switch to allow expansion of the smallest set of memcpy() via CGP. The DAG version checks for constant strings, so we need to do that here too. FWIW, the 2 constant test is not handled by LibCallSimplifier::optimizeMemCmp() because that code is limited to 8-bit constant arrays. LibCallSimplifier will also fail to optimize some 1 constant tests because its alignment requirements are too strict (shouldn't require alignment for a constant operand). Differential Revision: https://reviews.llvm.org/D34071 llvm-svn: 305734
* Change llvm-nm for Mach-O files to use dyld info in some cases when printing ↵Kevin Enderby2017-06-192-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | symbols. In order to reduce swift binary sizes, Apple is now stripping swift symbols from the nlist symbol table. llvm-nm currently only looks at the nlist symbol table and misses symbols that are present in dyld info. This makes it hard to know the set of symbols for a binary using just llvm-nm. Unless you know to run llvm-objdump -exports-trie that can output the exported symbols in the dyld info from the export trie, which does so but in a different format. Also moving forward the time may come a when a fully linked Mach-O file that uses dyld will no longer have an nlist symbol table to avoid duplicating the symbol information. This change adds three flags to llvm-nm, -add-dyldinfo, -no-dyldinfo, and -dyldinfo-only. The first, -add-dyldinfo, has the same effect as when the new bit in the Mach-O header, MH_NLIST_OUTOFSYNC_WITH_DYLDINFO, appears in a binary. In that it looks through the dyld info from the export trie and adds symbols to be printed that are not already in its internal SymbolList variable. The -no-dyldinfo option turns this behavior off. The -dyldinfo-only option only looks at the dyld information and recreates the symbol table from the dyld info from the export trie and binding information. As if it the Mach-O file had no nlist symbol table. Also fixed a few bugs with Mach-O N_INDR symbols not correctly printing the indirect name, or in the same format as the old nm-classic program. rdar://32021551 llvm-svn: 305733
* Improve profile-guided heuristics to use estimated trip count.Taewook Oh2017-06-192-26/+91
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Existing heuristic uses the ratio between the function entry frequency and the loop invocation frequency to find cold loops. However, even if the loop executes frequently, if it has a small trip count per each invocation, vectorization is not beneficial. On the other hand, even if the loop invocation frequency is much smaller than the function invocation frequency, if the trip count is high it is still beneficial to vectorize the loop. This patch uses estimated trip count computed from the profile metadata as a primary metric to determine coldness of the loop. If the estimated trip count cannot be computed, it falls back to the original heuristics. Reviewers: Ayal, mssimpso, mkuper, danielcdh, wmi, tejohnson Reviewed By: tejohnson Subscribers: tejohnson, mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D32451 llvm-svn: 305729
* [InstCombine] Make sure AddReachableCodeToWorklist sets MadeIRChangeBjorn Pettersson2017-06-192-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Some optimizations in AddReachableCodeToWorklist did not update the MadeIRChange state. This could happen both when removing trivially dead instructions (DCE) and at constant folds. It is essential that changes to the IR is reported correctly, since for example InstCombinePass::run() will indicate that all analyses are preserved otherwise. And the CGPassManager determines if the CallGraph is up-to-date based on status from InstructionCombiningPass::runOnFunction(). The new test case early_dce_clobbers_callgraph.ll is a reproducer for some asserts that started to trigger after changes in the inliner in r305245. With this patch the test case passes again. Reviewers: sanjoy, craig.topper, dblaikie Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34346 llvm-svn: 305725
* Revert r304824 "Fix PR23384 (part 3 of 3)"Hans Wennborg2017-06-1913-93/+89
| | | | | | | | | | | | | | | | | This seems to be interacting badly with ASan somehow, causing false reports of heap-buffer overflows: PR33514. > Summary: > The patch makes instruction count the highest priority for > LSR solution for X86 (previously registers had highest priority). > > Reviewers: qcolombet > > Differential Revision: http://reviews.llvm.org/D30562 > > From: Evgeny Stupachenko <evstupac@gmail.com> llvm-svn: 305720
* [CodeView] Fix dumping of public symbol record flagsReid Kleckner2017-06-191-2/+2
| | | | | | | I noticed nonsensical type information while dumping PDBs produced by MSVC. llvm-svn: 305708
* [InstCombine] Cleanup some duplicated one use checksCraig Topper2017-06-192-4/+4
| | | | | | | | | | | | | | | | | | | Summary: These 4 patterns have the same one use check repeated twice for each. Once without a cast and one with. But the cast has no effect on what method is called. For the OR case I believe it is always profitable regardless of the number of uses since we'll never increase the instruction count. For the AND case I believe it is profitable if the pair of xors has one use such that we'll get rid of it completely. Or if the C value is something freely invertible, in which case the not doesn't cost anything. Reviewers: spatel, majnemer Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34308 llvm-svn: 305705
* [Reassociate] Support some reassociation of vector xorsCraig Topper2017-06-191-4/+14
| | | | | | | | | | | | | | | | | Summary: Currently we don't try to do anything with vector xors. This patch adds support for removing duplicate pairs from a chain of vector xors as its pretty easy to support. We still dont' try to combine the xors with and/ors, but I might try that in a future patch. Reviewers: mcrosier, davide, resistor Reviewed By: mcrosier Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34338 llvm-svn: 305704
* [AMDGPU][mc][tests][NFC] Bulk ISA tests: Massive update. Add Gfx9 dasm tests.Artem Tamazov2017-06-195-82692/+259228
| | | | | | | | | | | A new Gfx9 dasm test added with approx 29000 cases. Existing tests extended by (approx.): * Gfx7 asm: 5000 test cases * Gfx8 asm: 5000 test cases * Gfx9 asm: 14400 test cases * Gfx8 dasm: 5200 test cases llvm-svn: 305702
* [JumpThreading][LVI] Invalidate LVI information after blocks are mergedAnna Thomas2017-06-191-0/+87
| | | | | | | | | | | | | | | | | | | Summary: After a single predecessor is merged into a basic block, we need to invalidate the LVI information for the new merged block, when LVI is not provably true for all of instructions in the new block. The test cases added show the correct LVI information using the LVI printer pass. Reviewers: reames, dberlin, davide, sanjoy Reviewed by: dberlin, davide Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34108 llvm-svn: 305699
* [TRE] Improve code motion in TRE, use AA to tell whether a load can be moved ↵Xin Tong2017-06-191-0/+27
| | | | | | | | | | | | | | | | before a call that writes to memory. Summary: use AA to tell whether a load can be moved before a call that writes to memory. Reviewers: dberlin, davide, sanjoy, hfinkel Reviewed By: hfinkel Subscribers: hfinkel, llvm-commits Differential Revision: https://reviews.llvm.org/D34115 llvm-svn: 305698
* Add test for store merge with noimplicitfloatNirav Dave2017-06-191-0/+23
| | | | llvm-svn: 305697
* AMDGPU/GlobalISel: Mark G_BITCAST s32 <--> <2 x s16> legalTom Stellard2017-06-191-0/+23
| | | | | | | | | | | | Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D34129 llvm-svn: 305692
* [GlobalISel][X86] Fold FI/G_GEP into LDR/STR instruction addressing mode.Igor Breger2017-06-197-171/+206
| | | | | | | | | | | | | | Summary: Implement some of the simplest addressing modes.It should help to test ABI. Reviewers: zvi, guyblank Reviewed By: guyblank Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D33888 llvm-svn: 305691
* [ARM] GlobalISel: Support G_ICMP for s8 and s16Diana Picus2017-06-192-3/+74
| | | | | | Widen to s32 (like all other binary ops). llvm-svn: 305683
* [ARM] GlobalISel: Support G_ICMP for i32 and pointersDiana Picus2017-06-194-0/+457
| | | | | | | | | | | | | | Add support throughout the pipeline: - mark as legal for s32 and pointers - map to GPRs - lower to a sequence of instructions, which moves 0 or 1 into the result register based on the flags set by a CMPrr We have copied from FastISel a helper function which maps CmpInst predicates into ARMCC codes. Ideally, we should be able to move it somewhere that both FastISel and GlobalISel can use. llvm-svn: 305672
* [X86] Simplify vector-shuffle-v48 test. NFC.Guy Blank2017-06-191-42/+39
| | | | llvm-svn: 305670
* [SCEV] Teach SCEVExpander to expand BinPowMax Kazantsev2017-06-191-0/+264
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current implementation of SCEVExpander demonstrates a very naive behavior when it deals with power calculation. For example, a SCEV for x^8 looks like (x * x * x * x * x * x * x * x) If we try to expand it, it generates a very straightforward sequence of muls, like: x2 = mul x, x x3 = mul x2, x x4 = mul x3, x ... x8 = mul x7, x This is a non-efficient way of doing that. A better way is to generate a sequence of binary power calculation. In this case the expanded calculation will look like: x2 = mul x, x x4 = mul x2, x2 x8 = mul x4, x4 In some cases the code size reduction for such SCEVs is dramatic. If we had a loop: x = a; for (int i = 0; i < 3; i++) x = x * x; And this loop have been fully unrolled, we have something like: x = a; x2 = x * x; x4 = x2 * x2; x8 = x4 * x4; The SCEV for x8 is the same as in example above, and if we for some reason want to expand it, we will generate naively 7 multiplications instead of 3. The BinPow expansion algorithm here allows to keep code size reasonable. This patch teaches SCEV Expander to generate a sequence of BinPow multiplications if we have repeating arguments in SCEVMulExpressions. Differential Revision: https://reviews.llvm.org/D34025 llvm-svn: 305663
* NewGVN: Fix PR 33461, caused by slightly overzealous verification.Daniel Berlin2017-06-191-0/+36
| | | | llvm-svn: 305657
* [x86] specify triples and auto-generate complete checks; NFCSanjay Patel2017-06-183-80/+174
| | | | llvm-svn: 305656
* [x86] specify triples and auto-generate complete checks; NFCSanjay Patel2017-06-184-122/+244
| | | | llvm-svn: 305655
* [x86] specify triple and auto-generate checks; NFCSanjay Patel2017-06-183-86/+182
| | | | llvm-svn: 305654
* x86] adjust test constants to maintain coverage; NFCSanjay Patel2017-06-184-33/+33
| | | | | | Increment (add 1) could be transformed to sub -1, and we'd lose coverage for these patterns. llvm-svn: 305646
* [x86] adjust test constants to maintain coverage; NFCSanjay Patel2017-06-181-7/+7
| | | | | | Increment (add 1) could be transformed to sub -1, and we'd lose coverage for these patterns. llvm-svn: 305645
* [x86] adjust test constants to maintain coverage; NFCSanjay Patel2017-06-181-10/+10
| | | | | | Increment (add 1) could be transformed to sub -1, and we'd lose coverage for these patterns. llvm-svn: 305644
* Add argmononly attribute to strlen and wcslen, i.e. they only read memory ↵Xin Tong2017-06-182-3/+23
| | | | | | | | | | | | | | | | (string) passed to them. Summary: This allows strlen to be moved out of the loop in case its argument is not modified in the loop in LICM. Reviewers: hfinkel, davide, sanjoy, dberlin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34323 llvm-svn: 305641
* [SROA] Add support for non-integral pointersSanjoy Das2017-06-171-0/+46
| | | | | | | | | | | | | | Summary: C.f. http://llvm.org/docs/LangRef.html#non-integral-pointer-type Reviewers: chandlerc, loladiro Reviewed By: loladiro Subscribers: reames, loladiro, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D32203 llvm-svn: 305639
* RegScavenging: Add scavengeRegisterBackwards()Matthias Braun2017-06-1712-117/+238
| | | | | | | | | | | | | | | | | | | Re-apply r276044/r279124/r305516. Fixed a problem where we would refuse to place spills as the very first instruciton of a basic block and thus artifically increase pressure (test in test/CodeGen/PowerPC/scavenging.mir:spill_at_begin) This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 305625
* [SelectionDAG] Update Loop info after splitting critical edges.Davide Italiano2017-06-171-0/+27
| | | | | | The analysis is expected to be preserved by SelectionDAG. llvm-svn: 305621
* [InstCombine] Make FPMathOperator working with ConstantExpression(s).Davide Italiano2017-06-171-0/+15
| | | | | | | | Fixes PR33453. Differential Revision: https://reviews.llvm.org/D34303 llvm-svn: 305618
* [WebAssembly] Use __stack_pointer global when writing wasm binarySam Clegg2017-06-166-49/+69
| | | | | | | | | | | | | | | | | | This ensures that symbolic relocations are generated for stack pointer manipulations. These relocations are of type R_WEBASSEMBLY_GLOBAL_INDEX_LEB. This change also adds support for reading relocations of this type in WasmObjectFile.cpp. Since its a globally imported symbol this does mean that the get_global/set_global instruction won't be valid until the objects are linked that global used in no longer an imported global. Differential Revision: https://reviews.llvm.org/D34172 llvm-svn: 305616
* obj2yaml: Improve error reportingSam Clegg2017-06-163-2/+6
| | | | | | | | | | Previously only the error codes were reported which meant that useful information about malformed inputs was not shown. Differential Revision: https://reviews.llvm.org/D34008 llvm-svn: 305609
* Revert rL305578. There is still some buildbot failure to be fixed.Wei Mi2017-06-163-135/+4
| | | | llvm-svn: 305603
* Move testcase into the target-appropriate subdirectory.Adrian Prantl2017-06-161-0/+0
| | | | llvm-svn: 305602
* Improve the accuracy of variable ranges .debug_loc location lists.Adrian Prantl2017-06-169-60/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the following motivating example bool c(); void f(); bool start() { bool result = c(); if (!c()) { result = false; goto exit; } f(); result = true; exit: return result; } we would previously generate a single DW_AT_const_value(1) because only the DBG_VALUE in the second-to-last basic block survived codegen. This patch improves the heuristic used to determine when a DBG_VALUE is available at the beginning of its variable's enclosing lexical scope: - Stop giving singular constants blanket permission to take over the entire scope. There is still a special case for constants in the function prologue that we also miight want to retire later. - Use the lexical scope information to determine available-at-entry instead of proximity to the function prologue. After this patch we generate a location list with a more accurate narrower availability for the constant true value. As a pleasant side effect, we also generate inline locations instead of location lists where a loacation covers the entire range of the enclosing lexical scope. Measured on compiling llc with four targets this doesn't have an effect on compile time and reduces the size of the debug info for llc by ~600K. rdar://problem/30286912 llvm-svn: 305599
* [DWARF] Corrected behavior for when no .apple_names section is present in ↵Spyridoula Gravani2017-06-162-1/+175
| | | | | | | | | | the object. The verifier should not output any message in such a case. Added test case with no .apple_name section in the file to verify new functionality. Made existing test case more specific. llvm-svn: 305597
* [InstCombine] Set correct insertion point for selects generated while ↵Anna Thomas2017-06-161-0/+29
| | | | | | | | | | | | | | | | | | | | | | folding phis Summary: When we fold vector constants that are operands of phi's that feed into select, we need to set the correct insertion point for the *new* selects that get generated. The correct insertion point is the incoming block for the phi. Such cases can occur with patch r298845, which fixed folding of vector constants, but the new selects could be inserted incorrectly (as the added test case shows). Reviewers: majnemer, spatel, sanjoy Reviewed by: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34162 llvm-svn: 305591
* Change YAML traits for vector<string> to flow_vector.Evgeniy Stepanov2017-06-161-7/+2
| | | | | | | This is a workaround for an ODR conflict with the definition in AMDGPUCodeObjectMetadata.cpp. llvm-svn: 305584
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