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| author | Igor Breger <igor.breger@intel.com> | 2017-06-20 09:15:10 +0000 |
|---|---|---|
| committer | Igor Breger <igor.breger@intel.com> | 2017-06-20 09:15:10 +0000 |
| commit | 1dcd5e8dc8274ede357868577abd7ac32f9b3bd9 (patch) | |
| tree | 5268e52fc26c04d296e0695d85f04d9a16f38ffa /llvm/test | |
| parent | 14535f0fc2978338071818dd2701e70ac4917126 (diff) | |
| download | bcm5719-llvm-1dcd5e8dc8274ede357868577abd7ac32f9b3bd9.tar.gz bcm5719-llvm-1dcd5e8dc8274ede357868577abd7ac32f9b3bd9.zip | |
[GlobalISel][X86] Get correct RegClass for given RegBank.
Summary:
In some cases RegClass depends on target feature. Hight (16-31) vector registers exist only if AVX512f available.
Split from https://reviews.llvm.org/D33665
Reviewers: qcolombet, t.p.northover, zvi, guyblank
Reviewed By: t.p.northover, guyblank
Subscribers: guyblank, rovka, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D33952
Conflicts:
test/CodeGen/X86/GlobalISel/select-memop-scalar.mir
llvm-svn: 305784
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir | 24 |
1 files changed, 18 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir index 9aaeb09b120..de79aac9f30 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir @@ -354,10 +354,16 @@ name: test_store_float alignment: 4 legalized: true regBankSelected: true +# NO_AVX512F: registers: +# NO_AVX512F-NEXT: - { id: 0, class: fr32, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 2, class: gr32, preferred-register: '' } +# +# AVX512ALL: registers: +# AVX512ALL-NEXT: - { id: 0, class: fr32x, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } registers: -# ALL: - { id: 0, class: fr32x, preferred-register: '' } -# ALL: - { id: 1, class: gr64, preferred-register: '' } -# ALL: - { id: 2, class: gr32, preferred-register: '' } - { id: 0, class: vecr } - { id: 1, class: gpr } - { id: 2, class: gpr } @@ -413,10 +419,16 @@ name: test_store_double alignment: 4 legalized: true regBankSelected: true +# NO_AVX512F: registers: +# NO_AVX512F-NEXT: - { id: 0, class: fr64, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 2, class: gr64, preferred-register: '' } +# +# AVX512ALL: registers: +# AVX512ALL-NEXT: - { id: 0, class: fr64x, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' } registers: -# ALL: - { id: 0, class: fr64x, preferred-register: '' } -# ALL: - { id: 1, class: gr64, preferred-register: '' } -# ALL: - { id: 2, class: gr64, preferred-register: '' } - { id: 0, class: vecr } - { id: 1, class: gpr } - { id: 2, class: gpr } |
