diff options
| author | Sanjoy Das <sanjoy@playingwithpointers.com> | 2017-06-19 22:35:48 +0000 |
|---|---|---|
| committer | Sanjoy Das <sanjoy@playingwithpointers.com> | 2017-06-19 22:35:48 +0000 |
| commit | 7ba830d61cfe8b4cfd8c61b7bbb6e2fa89677952 (patch) | |
| tree | bdd8b29341a4eb71b0d6a4c233deebb65a7f4d1b /llvm/test | |
| parent | de6cce2236c53f08107ab60dc47f3b7e4f5cc939 (diff) | |
| download | bcm5719-llvm-7ba830d61cfe8b4cfd8c61b7bbb6e2fa89677952.tar.gz bcm5719-llvm-7ba830d61cfe8b4cfd8c61b7bbb6e2fa89677952.zip | |
Fix machine instruction in test case
The AMD64rm instruction used in the test case was incorrect. Since
the first input register to AND64rm is tied to output register, they
must be the same.
Thanks for Jesper Antonsson for pointing this out!
llvm-svn: 305756
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/X86/implicit-null-checks.mir | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/X86/implicit-null-checks.mir b/llvm/test/CodeGen/X86/implicit-null-checks.mir index b05c4467d30..6efc965a694 100644 --- a/llvm/test/CodeGen/X86/implicit-null-checks.mir +++ b/llvm/test/CodeGen/X86/implicit-null-checks.mir @@ -544,7 +544,7 @@ liveins: - { reg: '%rsi' } # CHECK: bb.0.entry: # CHECK: %rbx = MOV64rr %rdx -# CHECK-NEXT: %rdi = FAULTING_OP 1, %bb.3.is_null, {{[0-9]+}}, %rbx, %rdi, 1, _, 0, _, implicit-def %eflags :: (load 4 from %ir.x) +# CHECK-NEXT: %rbx = FAULTING_OP 1, %bb.3.is_null, {{[0-9]+}}, %rbx, %rdi, 1, _, 0, _, implicit-def %eflags :: (load 4 from %ir.x) body: | bb.0.entry: @@ -557,9 +557,9 @@ body: | liveins: %rsi, %rdi, %rdx %rbx = MOV64rr %rdx - %rdi = AND64rm killed %rbx, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x) + %rbx = AND64rm killed %rbx, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x) %rdx = MOV64ri 0 - CMP64rr killed %rdi, killed %rsi, implicit-def %eflags + CMP64rr killed %rbx, killed %rsi, implicit-def %eflags JE_1 %bb.4.ret_100, implicit %eflags bb.2.ret_200: |
