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* [DeadArgumentElimination] Preserve llvm.dbg.values's first argumentPetar Jovanovic2018-01-301-0/+135
| | | | | | | | | | | | | When removing return value Dead Argument Elimination pass clobbers first llvm.dbg.value’s argument for live arguments of that function by replacing it with nullptr. In the next pass it will be deleted, so debug location about those arguments are lost. This change fixes it. Patch by Djordje Todorovic. Differential Revision: https://reviews.llvm.org/D42541 llvm-svn: 323784
* CodeGen: support an extension to pass linker options on ELFSaleem Abdulrasool2018-01-303-0/+41
| | | | | | | | | | | | | | | | | | Introduce an extension to support passing linker options to the linker. These would be ignored by older linkers, but newer linkers which support this feature would be able to process the linker. Emit a special discarded section `.linker-option`. The content of this section is a pair of strings (key, value). The key is a type identifier for the parameter. This allows for an argument free parameter that will be processed by the linker with the value being the parameter. As an example, `lib` identifies a library to be linked against, traditionally the `-l` argument for Unix-based linkers with the parameter being the library name. Thanks to James Henderson, Cary Coutant, Rafael Espinolda, Sean Silva for the valuable discussion on the design of this feature. llvm-svn: 323783
* [AArch64] Add new target feature to fuse address generation with load or storeEvandro Menezes2018-01-301-0/+112
| | | | | | | | | This feature enables the fusion of the address generation and a corresponding load or store together. Differential revision: https://reviews.llvm.org/D42393 llvm-svn: 323782
* [mips] Fix incorrect sign extension for fpowi libcallSimon Dardis2018-01-301-0/+65
| | | | | | | | | | | | | | | | | PR36061 showed that during the expansion of ISD::FPOWI, that there was an incorrect zero extension of the integer argument which for MIPS64 would then give incorrect results. Address this with the existing mechanism for correcting sign extensions. This resolves PR36061. Thanks to James Cowgill for reporting the issue! Reviewers: atanasyan, hfinkel Differential Revision: https://reviews.llvm.org/D42537 llvm-svn: 323781
* Re-commit : [PowerPC] Add handling for ColdCC calling convention and a pass ↵Zaara Syeda2018-01-306-1/+221
| | | | | | | | | | | | | | | | | | | | | to mark candidates with coldcc attribute. This recommits r322721 reverted due to sanitizer memory leak build bot failures. Original commit message: This patch adds support for the coldcc calling convention for Power. This changes the set of non-volatile registers. It includes a pass to stress test the implementation by marking all static directly called functions with the coldcc attribute through the option -enable-coldcc-stress-test. It also includes an option, -ppc-enable-coldcc, to add the coldcc attribute to functions which are cold at all call sites based on BlockFrequencyInfo when the containing function does not call any non cold functions. Differential Revision: https://reviews.llvm.org/D38413 llvm-svn: 323778
* [X86][AVX512] Add VBMI target shuffle-trunc tests Simon Pilgrim2018-01-303-0/+325
| | | | llvm-svn: 323776
* [AArch64] Update test cases for Exynos M3Evandro Menezes2018-01-304-42/+106
| | | | | | Update any test case relevant for Exynos M3. llvm-svn: 323775
* [AArch64] Add pipeline model for Exynos M3Evandro Menezes2018-01-304-3/+13
| | | | | | | | Add the scheduling and cost model for Exynos M3. Differential revision: https://reviews.llvm.org/D42387 llvm-svn: 323773
* [RS4GC] Handle call/invoke instructions as base defining values of vectorsDaniel Neilson2018-01-302-0/+42
| | | | | | | | | | | | | | | | | | Summary: There's an asymmetry in the definitions of findBaseDefiningValueOfVector() and findBaseDefiningValue() of RS4GC. The later handles call and invoke instructions, and the former does not. This appears to be simple oversight. This patch remedies the oversight by adding the call and invoke cases to findBaseDefiningValueOfVector(). Reviewers: DaniilSuchkov, anna Reviewed By: anna Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42653 llvm-svn: 323764
* [X86FixupBWInsts] mir-simplify fixup-bw-inst.mir test. NFC.Andrei Elovikov2018-01-301-99/+5
| | | | llvm-svn: 323762
* Revert "[X86] Avoid using high register trick for test instruction"Eric Liu2018-01-303-7/+14
| | | | | | This reverts commit r323690. This causes crash in llc. See the original commit thread for details. llvm-svn: 323761
* [X86] Add test case for PR32690Simon Pilgrim2018-01-301-0/+27
| | | | llvm-svn: 323760
* [DSE] make sure memory is not modified before partial store merging (PR36129)Sanjay Patel2018-01-301-2/+4
| | | | | | | | | | | | We missed a critical check in D30703. We must make sure that no intermediate store is sitting between the stores that we want to merge. This should fix: https://bugs.llvm.org/show_bug.cgi?id=36129 Differential Revision: https://reviews.llvm.org/D42663 llvm-svn: 323759
* Change simple-register-allocation-read-undef.mir so that it doesn't fail if ↵Amaury Sechet2018-01-301-1/+1
| | | | | | the file path contains 'dead' . NFC llvm-svn: 323748
* [ARM GlobalISel] Add inst selector tests for G_SITOFP and G_UITOFPDiana Picus2018-01-301-0/+113
| | | | | | These are handled by the TableGen'erated code. llvm-svn: 323732
* [ARM GlobalISel] Map G_SITOFP and G_UITOFPDiana Picus2018-01-301-0/+91
| | | | | | | Straightforward mapping (integer operand to GPR, floating point operand to FPR). llvm-svn: 323731
* [ARM GlobalISel] Legalize G_SITOFP and G_UITOFPDiana Picus2018-01-301-0/+143
| | | | | | | | Legal if we have hardware support, libcall otherwise. Also add supporting code to the legalizer helper for libcalls. llvm-svn: 323730
* [ARM GlobalISel] Add inst selector tests for G_FPTOSI and G_FPTOUIDiana Picus2018-01-301-0/+113
| | | | | | The work is done by the TableGen'erated code. llvm-svn: 323728
* [ARM GlobalISel] Map G_FPTOSI and G_FPTOUIDiana Picus2018-01-301-0/+91
| | | | | | | Straightforward mapping (integer operand goes to GPR, floating point operand goes to FPR). llvm-svn: 323727
* [ARM GlobalISel] Legalize G_FPTOSI and G_FPTOUIDiana Picus2018-01-301-0/+143
| | | | | | | | | Legal if we have hardware support for floating point, libcalls otherwise. Also add the necessary support for libcalls in the legalizer helper. llvm-svn: 323726
* [X86] Auto-generate complete checks. NFCCraig Topper2018-01-301-125/+330
| | | | llvm-svn: 323724
* [DWARF] Corrected test committed in r323670 to use llc instead of llc_dwarf ↵Wolfgang Pieb2018-01-301-2/+2
| | | | | | to avoid multiple triples. llvm-svn: 323721
* [InstSimplify] (X * Y) / Y --> X for relaxed floating-point opsSanjay Patel2018-01-301-0/+34
| | | | | | | | | This is the FP counterpart that was mentioned in PR35709: https://bugs.llvm.org/show_bug.cgi?id=35709 Differential Revision: https://reviews.llvm.org/D42385 llvm-svn: 323716
* [SelectionDAG]: Ignore "returned" in the presence of an implicit sret.Dan Gohman2018-01-301-0/+20
| | | | | | | | | | | | | | | | When a function return value can't be directly lowered, such as returning an i128 on WebAssembly, as indicated by the CanLowerReturn target hook, SelectionDAGBuilder can translate it to return the value through a hidden sret-like argument. If such a function has an argument with the "returned" attribute, the attribute can't be automatically lowered, because the function no longer has a normal return value. For now, just discard the "returned" attribute. This fixes PR36128. llvm-svn: 323715
* [RAFast] Don't dereference MBB::endQuentin Colombet2018-01-291-0/+26
| | | | | | | | | | | | | | | | When RAFast sees liveins in on a basic block, it uses that information to initialize the availability of the registers. The called method uses an instruction as one of its argument and in the liveins case, RAFast was dereferencing MBB::begin which can be MBB::end for empty basic block. Change the API of definePhysReg to use MachineBasicBlock::iterator instead of MachineInstr so that we don't dereference an invalid iterator while making the call. rdar://problem/36952401 llvm-svn: 323710
* [X86] Use VMOVDQA64 for aligned vXi32 stores.Craig Topper2018-01-291-1/+1
| | | | | | I meant to do this with the unaligned stores in r322820, but looks like I missed it. llvm-svn: 323708
* AMDGPU: Allow a SGPR for the conditional KILL operandMarek Olsak2018-01-291-0/+17
| | | | | | | | | | | | | | | | | | Patch by: Bas Nieuwenhuizen Just use the _e64 variant if needed. This should be possible as per def : Pat < (int_amdgcn_kill (i1 (setcc f32:$src, InlineFPImm<f32>:$imm, cond:$cond))), (SI_KILL_F32_COND_IMM_PSEUDO $src, (bitcast_fpimm_to_i32 $imm), (cond_as_i32imm $cond)) > ; I don't think we can get an immediate for the other operand for which we need the second 32-bit word. https://reviews.llvm.org/D42302 llvm-svn: 323706
* [DSE] add test for PR36129; NFCSanjay Patel2018-01-291-0/+15
| | | | | | | We can miscompile because we're not checking is the memory might me modified between the seemingly redundant store ops. llvm-svn: 323704
* [X86] Add FeaturePOPCNTFalseDeps to skylake server CPU to match skylake client.Craig Topper2018-01-291-0/+1
| | | | llvm-svn: 323700
* [X86] Emit 11-byte or 15-byte NOPs on recent AMD targets, else default to ↵Simon Pilgrim2018-01-296-27/+51
| | | | | | | | | | | | 10-byte NOPs (PR22965) We currently emit up to 15-byte NOPs on all targets (apart from Silvermont), which stalls performance on some targets with decoders that struggle with 2 or 3 more '66' prefixes. This patch flags recent AMD targets (btver1/znver1) to still emit 15-byte NOPs and bdver* targets to emit 11-byte NOPs. All other targets now emit 10-byte NOPs apart from SilverMont CPUs which still emit 7-byte NOPS. Differential Revision: https://reviews.llvm.org/D42616 llvm-svn: 323693
* [ARM][GISel] PR35965 Constrain RegClasses of nested instructions built from ↵Daniel Sanders2018-01-292-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Dst Pattern Summary: Apparently, we missed on constraining register classes of VReg-operands of all the instructions built from a destination pattern but the root (top-level) one. The issue exposed itself while selecting G_FPTOSI for armv7: the corresponding pattern generates VTOSIZS wrapped into COPY_TO_REGCLASS, so top-level COPY_TO_REGCLASS gets properly constrained, while nested VTOSIZS (or rather its destination virtual register to be exact) does not. Fixing this by issuing GIR_ConstrainSelectedInstOperands for every nested GIR_BuildMI. https://bugs.llvm.org/show_bug.cgi?id=35965 rdar://problem/36886530 Patch by Roman Tereshin Reviewers: dsanders, qcolombet, rovka, bogner, aditya_nandakumar, volkan Reviewed By: dsanders, qcolombet, rovka Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D42565 llvm-svn: 323692
* [DWARFv5] Re-enable dumping a line table with no CU.Paul Robinson2018-01-291-7/+14
| | | | | | | | | | | r323476 added support for DW_FORM_line_strp, and incorrectly made that depend on having a DWARFUnit available. We shouldn't be tracking .debug_line_str in DWARFUnit after all. After this patch, I can do an NFC follow up and undo a bunch of the "plumbing" part of r323476. Differential Revision: https://reviews.llvm.org/D42609 llvm-svn: 323691
* [X86] Avoid using high register trick for test instructionAmaury Sechet2018-01-293-14/+7
| | | | | | | | | | | | | | | Summary: It seems it's main effect is to create addition copies when values are inr register that do not support this trick, which increase register pressure and makes the code bigger. The main noteworthy regression I was able to observe was pattern of the type (setcc (trunc (and X, C)), 0) where C is such as it would benefit from the hi register trick. To prevent this, a new pattern is added to materialize such pattern using a 32 bits test. This has the added benefit of working with any constant that is materializable as a 32bits immediate, not just the ones that can leverage the high register trick, as demonstrated by the test case in test-shrink.ll using the constant 2049 . Reviewers: craig.topper, niravd, spatel, hfinkel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42646 llvm-svn: 323690
* [X86] Add test case to ensure testw is generated when optimizing for size. NFCAmaury Sechet2018-01-291-0/+44
| | | | llvm-svn: 323687
* Revert "AArch64: Omit callframe setup/destroy when not necessary"Jun Bum Lim2018-01-298-74/+63
| | | | | | | | This reverts commit r322917 due to multiple performance regressions in spec2006 and spec2017. XFAILed llvm/test/CodeGen/AArch64/big-callframe.ll which initially motivated this change. llvm-svn: 323683
* Improve testcase.Rafael Espindola2018-01-291-21/+13
| | | | | | | | We now test that pic and static produce different results for bar. The function names were demangled. The attributes are written inline. llvm-svn: 323680
* [AMDGPU][X86][Mips] Make sure renamable bit not set for reserved regsGeoff Berry2018-01-291-1/+1
| | | | | | | | | Summary: Fix a few places that were modifying code after register allocation to set the renamable bit correctly to avoid failing the validation added in D42449. llvm-svn: 323675
* [X86] Don't create SHRUNKBLEND when the condition is used by the true or ↵Craig Topper2018-01-291-32/+35
| | | | | | | | | | false operand of the vselect. Fixes PR34592. Differential Revision: https://reviews.llvm.org/D42628 llvm-svn: 323672
* [X86] Add test case for pr34592Craig Topper2018-01-291-0/+68
| | | | llvm-svn: 323671
* [DWARF] Recommitting a test reverted in r323560. Moved to x86 directory with ↵Wolfgang Pieb2018-01-291-0/+157
| | | | | | | | explicit triple. ELF support is required for type units. llvm-svn: 323670
* Add test case for truncated and promotion to test. NFCAmaury Sechet2018-01-291-0/+49
| | | | llvm-svn: 323663
* [SLP] Fix for PR32086: Count InsertElementInstr of the same elements as shuffle.Alexey Bataev2018-01-293-31/+31
| | | | | | | | | | | | | | | | | Summary: If the same value is going to be vectorized several times in the same tree entry, this entry is considered to be a gather entry and cost of this gather is counter as cost of InsertElementInstrs for each gathered value. But we can consider these elements as ShuffleInstr with SK_PermuteSingle shuffle kind. Reviewers: spatel, RKSimon, mkuper, hfinkel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38697 llvm-svn: 323662
* [SLP] Add a test with extract for PR32086, NFC.Alexey Bataev2018-01-291-0/+33
| | | | llvm-svn: 323661
* [dsymutil] Generate Apple accelerator tablesJonas Devlieghere2018-01-294-2/+245
| | | | | | | | | | | This patch adds support for generating accelerator tables in dsymutil. This feature was already present in our internal repository but not yet upstreamed because it requires changes to the Apple accelerator table implementation. Differential revision: https://reviews.llvm.org/D42501 llvm-svn: 323655
* [AMDGPU][MC] Corrected parsing of image opcode modifiers r128 and d16Dmitry Preobrazhensky2018-01-292-0/+26
| | | | | | | | | | | See bugs 36092, 36093: https://bugs.llvm.org/show_bug.cgi?id=36092 https://bugs.llvm.org/show_bug.cgi?id=36093 Differential Revision: https://reviews.llvm.org/D42583 Reviewers: vpykhtin, artem.tamazov, arsenm llvm-svn: 323651
* [DebugInfo] Fix fragment offset emission order for symbol locationsMikael Holmen2018-01-291-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When emitting the location for a global variable with fragmented debug expressions, make sure that the offset pieces, which represent optimized-out parts of the variable, are emitted before their succeeding fragments' expressions. Previously, if the succeeding fragment's location was a symbol, the offset piece was emitted after, rather than before, that symbol's expression. This effectively meant that the symbols were associated with the wrong parts of the variable. This fixes PR36085. Patch by: David Stenberg Reviewers: aprantl, probinson, dblaikie Reviewed By: aprantl Subscribers: JDevlieghere, llvm-commits Tags: #debug-info Differential Revision: https://reviews.llvm.org/D42527 llvm-svn: 323644
* [Sparc] Account for bias in stack readjustmentJonas Devlieghere2018-01-291-5/+11
| | | | | | | | | | | | | | | | | | | Summary: This was broken long ago in D12208, which failed to account for the fact that 64-bit SPARC uses a stack bias of 2047, and it is the *unbiased* value which should be aligned, not the biased one. This was seen to be an issue with Rust. Patch by: jrtc27 (James Clarke) Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: jacob_hansen, JDevlieghere, fhahn, fedor.sergeev, llvm-commits Differential Revision: https://reviews.llvm.org/D39425 llvm-svn: 323643
* Refactor dwarfdump -apple-names outputPavel Labath2018-01-293-51/+54
| | | | | | | | | | | | | | | | | | Summary: This modifies the dwarfdump output to align it with the new .debug_names dump. It also renames two header fields to match similar fields in the dwarf5 header. A couple of tests needed to be updated to match new output. The changes were fairly straight-forward, although not really automatable. Reviewers: JDevlieghere, aprantl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42415 llvm-svn: 323641
* [DebugInfo] Basic .debug_names dumping supportPavel Labath2018-01-291-0/+176
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This commit renames DWARFAcceleratorTable to AppleAcceleratorTable to free up the first name as an interface for the different accelerator tables. Then I add a DWARFDebugNames class for the dwarf5 table. Presently, the only common functionality of the two classes is the dump() method, because this is the only method that was necessary to implement dwarfdump -debug-names; and because the rest of the AppleAcceleratorTable interface does not directly transfer to the dwarf5 tables (the main reason for that is that the present interface assumes the tables are homogeneous, but the dwarf5 tables can have different keys associated with each entry). I expect to make the common interface richer as I add more functionality to the new class (and invent a way to represent it in generic way). In terms of sharing the implementation, I found the format of the two tables sufficiently different to frustrate any attempts to have common parsing or dumping code, so presently the implementations share just low level code for formatting dwarf constants. Reviewers: vleschuk, JDevlieghere, clayborg, aprantl, probinson, echristo, dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42297 llvm-svn: 323638
* [X86FixupBWInsts] Fix miscompilation if sibling sub-register is live.Andrei Elovikov2018-01-291-0/+45
| | | | | | | | | | | | | | Summary: The issues was found during D40524. Reviewers: andrew.w.kaylor, craig.topper, MatzeB Reviewed By: andrew.w.kaylor Subscribers: aivchenk, llvm-commits Differential Revision: https://reviews.llvm.org/D42533 llvm-svn: 323635
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