[AMDGPU][MC] Corrected parsing of image opcode modifiers r128 and d16

See bugs 36092, 36093:
    https://bugs.llvm.org/show_bug.cgi?id=36092
    https://bugs.llvm.org/show_bug.cgi?id=36093

Differential Revision: https://reviews.llvm.org/D42583

Reviewers: vpykhtin, artem.tamazov, arsenm
llvm-svn: 323651

2 files changed, 26 insertions, 0 deletions

diff --git a/llvm/test/MC/AMDGPU/mimg.s b/llvm/test/MC/AMDGPU/mimg.s
index 761eacd59b3..890e937ef0d 100644
--- a/llvm/test/MC/AMDGPU/mimg.s
+++ b/llvm/test/MC/AMDGPU/mimg.s
@@ -18,6 +18,16 @@ image_load    v[4:7], v[237:240], s[28:35] dmask:0x7 tfe
 // SICI: image_load v[4:7], v[237:240], s[28:35] dmask:0x7 tfe ; encoding: [0x00,0x07,0x01,0xf0,0xed,0x04,0x07,0x00]
 // VI:   image_load v[4:7], v[237:240], s[28:35] dmask:0x7 tfe ; encoding: [0x00,0x07,0x01,0xf0,0xed,0x04,0x07,0x00]
 
+// Verify support of all possible modifiers.
+// FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
+// FIXME: Check that d16 is not supported before VI
+image_load    v[5:6], v[1:4], s[8:15] dmask:0x1 unorm glc slc r128 tfe lwe da d16
+// VI:   image_load v[5:6], v[1:4], s[8:15] dmask:0x1 unorm glc slc r128 tfe lwe da d16 ; encoding: [0x00,0xf1,0x03,0xf2,0x01,0x05,0x02,0x80]
+
+// FIXME: Check that d16 is not supported before VI
+image_load v5, v[1:4], s[8:15] d16
+// VI:   image_load v5, v[1:4], s[8:15] d16 ; encoding: [0x00,0x00,0x00,0xf0,0x01,0x05,0x02,0x80]
+
 image_store   v[193:195], v[237:240], s[28:35] dmask:0x7 unorm
 // SICI: image_store v[193:195], v[237:240], s[28:35] dmask:0x7 unorm ; encoding: [0x00,0x17,0x20,0xf0,0xed,0xc1,0x07,0x00]
 // VI:   image_store v[193:195], v[237:240], s[28:35] dmask:0x7 unorm ; encoding: [0x00,0x17,0x20,0xf0,0xed,0xc1,0x07,0x00]
@@ -30,6 +40,16 @@ image_store   v[193:194], v[237:240], s[28:35] tfe
 // SICI: image_store v[193:194], v[237:240], s[28:35] tfe ; encoding: [0x00,0x00,0x21,0xf0,0xed,0xc1,0x07,0x00]
 // VI:   image_store v[193:194], v[237:240], s[28:35] tfe ; encoding: [0x00,0x00,0x21,0xf0,0xed,0xc1,0x07,0x00]
 
+// Verify support of all possible modifiers.
+// FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
+// FIXME: Check that d16 is not supported before VI
+image_store   v5, v[1:4], s[8:15] dmask:0x1 unorm glc slc r128 lwe da d16
+// VI:   image_store v5, v[1:4], s[8:15] dmask:0x1 unorm glc slc r128 lwe da d16 ; encoding: [0x00,0xf1,0x22,0xf2,0x01,0x05,0x02,0x80]
+
+// FIXME: Check that d16 is not supported before VI
+image_store    v5, v[1:4], s[8:15] d16
+// VI:   image_store v5, v[1:4], s[8:15] d16 ; encoding: [0x00,0x00,0x20,0xf0,0x01,0x05,0x02,0x80]
+
 //===----------------------------------------------------------------------===//
 // Image Sample
 //===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/Disassembler/AMDGPU/mimg_vi.txt b/llvm/test/MC/Disassembler/AMDGPU/mimg_vi.txt
index 1a4885d774a..10d2ce9a2dd 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/mimg_vi.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/mimg_vi.txt
@@ -28,6 +28,12 @@
 # VI: image_store v0, v1, s[0:7] dmask:0x1 unorm ; encoding: [0x00,0x11,0x20,0xf0,0x01,0x00,0x00,0x00]
 0x00 0x11 0x20 0xf0 0x01 0x00 0x00 0x00
 
+# Test all modifiers
+# FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
+# FIXME: This test is incorrect because tfe shall increase data size by 1.
+# VI: image_load v5, v1, s[8:15] dmask:0x1 unorm glc slc r128 tfe lwe da d16 ; encoding: [0x00,0xf1,0x03,0xf2,0x01,0x05,0x02,0x80]
+0x00,0xf1,0x03,0xf2,0x01,0x05,0x02,0x80
+
 # Test dmask == 0
 # VI: image_load v0, v4, s[8:15] unorm ; encoding: [0x00,0x10,0x00,0xf0,0x04,0x00,0x02,0x00]
 0x00 0x10 0x00 0xf0 0x04 0x00 0x02 0x00