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authorGeoff Berry <gberry@codeaurora.org>2018-01-29 18:47:48 +0000
committerGeoff Berry <gberry@codeaurora.org>2018-01-29 18:47:48 +0000
commitd37dc77b6e52d46f2388070f2fd530424b49a8cd (patch)
treefe09801732f33a3e4f05668d1eba70de4f02a05a /llvm/test
parentd5f76ad37fb235c684d551251eb8c0e204bde134 (diff)
downloadbcm5719-llvm-d37dc77b6e52d46f2388070f2fd530424b49a8cd.tar.gz
bcm5719-llvm-d37dc77b6e52d46f2388070f2fd530424b49a8cd.zip
[AMDGPU][X86][Mips] Make sure renamable bit not set for reserved regs
Summary: Fix a few places that were modifying code after register allocation to set the renamable bit correctly to avoid failing the validation added in D42449. llvm-svn: 323675
Diffstat (limited to 'llvm/test')
-rw-r--r--llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir b/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir
index 85ce251ac31..9939fa61820 100644
--- a/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir
+++ b/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir
@@ -40,7 +40,7 @@ stack:
constants:
body: |
bb.0.entry:
- renamable %zero = SLL_MMR6 killed renamable %zero, 0
+ %zero = SLL_MMR6 killed %zero, 0
JRC16_MM undef %ra, implicit %v0
...
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