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* [RuntimeDyld][MCJIT] Un-XFAIL some tests that were fixed by r279182.Lang Hames2016-08-1910-10/+10
| | | | llvm-svn: 279201
* Revert "RegScavenging: Add scavengeRegisterBackwards()"Matthias Braun2016-08-194-64/+36
| | | | | | | | | | | The ppc64 multistage bot fails on this. This reverts commit r279124. Also Revert "CodeGen: Add/Factor out LiveRegUnits class; NFCI" because it depends on the previous change This reverts commit r279171. llvm-svn: 279199
* [asan] Optimize store size in FunctionStackPoisoner::poisonRedZonesVitaly Buka2016-08-182-7/+7
| | | | | | | | | | | | Summary: Reduce store size to avoid leading and trailing zeros. Reviewers: kcc, eugenis Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23648 llvm-svn: 279178
* CodeGen: If Convert blocks that would form a diamond when tail-merged.Kyle Butt2016-08-182-4/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following function currently relies on tail-merging for if conversion to succeed. The common tail of cond_true and cond_false is extracted, and this then forms a diamond pattern that can be successfully if converted. If this block does not get extracted, either because tail-merging is disabled or the threshold is higher, we should still recognize this pattern and if-convert it. Fixed a regression in the original commit. Need to un-reverse branches after reversing them, or other conversions go awry. Regression on self-hosting bots with no obvious explanation. Tidied up range handling to be more obviously correct, but there was no smoking gun. define i32 @t2(i32 %a, i32 %b) nounwind { entry: %tmp1434 = icmp eq i32 %a, %b ; <i1> [#uses=1] br i1 %tmp1434, label %bb17, label %bb.outer bb.outer: ; preds = %cond_false, %entry %b_addr.021.0.ph = phi i32 [ %b, %entry ], [ %tmp10, %cond_false ] %a_addr.026.0.ph = phi i32 [ %a, %entry ], [ %a_addr.026.0, %cond_false ] br label %bb bb: ; preds = %cond_true, %bb.outer %indvar = phi i32 [ 0, %bb.outer ], [ %indvar.next, %cond_true ] %tmp. = sub i32 0, %b_addr.021.0.ph %tmp.40 = mul i32 %indvar, %tmp. %a_addr.026.0 = add i32 %tmp.40, %a_addr.026.0.ph %tmp3 = icmp sgt i32 %a_addr.026.0, %b_addr.021.0.ph br i1 %tmp3, label %cond_true, label %cond_false cond_true: ; preds = %bb %tmp7 = sub i32 %a_addr.026.0, %b_addr.021.0.ph %tmp1437 = icmp eq i32 %tmp7, %b_addr.021.0.ph %indvar.next = add i32 %indvar, 1 br i1 %tmp1437, label %bb17, label %bb cond_false: ; preds = %bb %tmp10 = sub i32 %b_addr.021.0.ph, %a_addr.026.0 %tmp14 = icmp eq i32 %a_addr.026.0, %tmp10 br i1 %tmp14, label %bb17, label %bb.outer bb17: ; preds = %cond_false, %cond_true, %entry %a_addr.026.1 = phi i32 [ %a, %entry ], [ %tmp7, %cond_true ], [ %a_addr.026.0, %cond_false ] ret i32 %a_addr.026.1 } Without tail-merging or diamond-tail if conversion: LBB1_1: @ %bb @ =>This Inner Loop Header: Depth=1 cmp r0, r1 ble LBB1_3 @ BB#2: @ %cond_true @ in Loop: Header=BB1_1 Depth=1 subs r0, r0, r1 cmp r1, r0 it ne cmpne r0, r1 bgt LBB1_4 LBB1_3: @ %cond_false @ in Loop: Header=BB1_1 Depth=1 subs r1, r1, r0 cmp r1, r0 bne LBB1_1 LBB1_4: @ %bb17 bx lr With diamond-tail if conversion, but without tail-merging: @ BB#0: @ %entry cmp r0, r1 it eq bxeq lr LBB1_1: @ %bb @ =>This Inner Loop Header: Depth=1 cmp r0, r1 ite le suble r1, r1, r0 subgt r0, r0, r1 cmp r1, r0 bne LBB1_1 @ BB#2: @ %bb17 bx lr llvm-svn: 279168
* llvm-objdump: Add Hexagon printer changes for -S/-l optionsHemant Kulkarni2016-08-183-0/+88
| | | | | | Differential Revision: https://reviews.llvm.org/D23521 llvm-svn: 279161
* [SystemZ] Use valid base/index regs for inline asmZhan Jun Liau2016-08-181-2/+2
| | | | | | | | | | | | | | | Summary: Inline asm memory constraints can have the base or index register be assigned to %r0 right now. Make sure that we assign only ADDR64 registers to the base and index. Reviewers: uweigand Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23367 llvm-svn: 279157
* AMDGPU/SI: Fix a test in wqm.ll to always use s_cbranch_vcc*Tom Stellard2016-08-181-7/+7
| | | | | | | | | | | | | | | Summary: We need to use floating-point compares to ensure that s_cbranch_vcc* instructions are always generated. With integer compares, future optimizations could cause s_cbranch_scc* to be generated instead. Reviewers: arsenm, nhaehnle Subscribers: llvm-commits, kzhuravl Differential Revision: https://reviews.llvm.org/D23401 llvm-svn: 279148
* Make cltz and cttz zero undef when the operand cannot be zero in InstCombineAmaury Sechet2016-08-181-0/+20
| | | | | | | | | | | | Summary: Also add popcount(n) == bitsize(n) -> n == -1 transformation. Reviewers: majnemer, spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23134 llvm-svn: 279141
* [InstCombine] use m_APInt to allow icmp (trunc X, Y), C folds for splat ↵Sanjay Patel2016-08-182-11/+4
| | | | | | | | | | | | | | constant vectors This is a sibling of: https://reviews.llvm.org/rL278859 https://reviews.llvm.org/rL278935 https://reviews.llvm.org/rL278945 https://reviews.llvm.org/rL279066 https://reviews.llvm.org/rL279077 https://reviews.llvm.org/rL279101 llvm-svn: 279133
* AMDGPU : Fix QSAD and MQSAD instructions' incorrect data type.Wei Ding2016-08-182-18/+18
| | | | | | Differential Revision: http://reviews.llvm.org/D23689 llvm-svn: 279126
* [SLP] Initialize VectorizedValue when gatheringMatthew Simpson2016-08-181-0/+95
| | | | | | | | | | | | | | | | | We abort building vectorizable trees in some cases (e.g., if the maximum recursion depth is reached, if the region size is too large, etc.). If this happens for a reduction, we can be left with a root entry that needs to be gathered. For these cases, we need make sure we actually set VectorizedValue to the resulting vector. This patch ensures we properly set VectorizedValue, and it also ensures the insertelement sequence generated for the gathers is inserted at the correct location. Reference: https://llvm.org/bugs/show_bug.cgi?id=28330 Differential Revison: https://reviews.llvm.org/D23410 llvm-svn: 279125
* RegScavenging: Add scavengeRegisterBackwards()Matthias Braun2016-08-184-36/+64
| | | | | | | | | | | | | | | | Re-apply r276044 with off-by-1 instruction fix for the reload placement. This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 279124
* [X86][SSE] Missed insertps shuffle patternsSimon Pilgrim2016-08-181-0/+36
| | | | llvm-svn: 279111
* [asan] Extend testVitaly Buka2016-08-181-3/+33
| | | | | | | | | | | | Summary: PR27453 Reviewers: eugenis Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23647 llvm-svn: 279109
* [AMDGPU] add s_incperflevel/s_decperflevel intrinsics.Valery Pykhtin2016-08-182-0/+86
| | | | | | Differential revision: https://reviews.llvm.org/D23666 llvm-svn: 279106
* Fix SystemZ compilation abort caused by negative AND maskElliot Colp2016-08-181-0/+22
| | | | | | | | | | Normally, when an AND with a constant is lowered to NILL, the constant value is truncated to 16 bits. However, since r274066, ANDs whose results are used in a shift are caught by a different pattern that does not truncate. The instruction printer expects a 16-bit unsigned immediate operand for NILL, so this results in an abort. This patch adds code to manually truncate the constant in this situation. The rest of the bits are then set, so we will detect a case for NILL "naturally" rather than using peephole optimizations. Differential Revision: http://reviews.llvm.org/D21854 llvm-svn: 279105
* AArch64: Don't call getIterator() on iteratorsDuncan P. N. Exon Smith2016-08-181-0/+29
| | | | | | | | | | | | | | | | | Remove an unnecessary round-trip: iterator => operator->() => getIterator() In some cases, the iterator is end(), so the dereference of operator-> is invalid (UB). The testcase only crashes with r278974 (currently reverted to investigate this), which adds an assertion for invalid dereferences of ilist nodes. Fixes PR29035. llvm-svn: 279104
* [InstCombine] use m_APInt to allow icmp (udiv X, Y), C folds for splat ↵Sanjay Patel2016-08-181-16/+7
| | | | | | | | | | | | | constant vectors This is a sibling of: https://reviews.llvm.org/rL278859 https://reviews.llvm.org/rL278935 https://reviews.llvm.org/rL278945 https://reviews.llvm.org/rL279066 https://reviews.llvm.org/rL279077 llvm-svn: 279101
* [WebAssembly] Disable the store-results optimization.Dan Gohman2016-08-186-134/+70
| | | | | | | | | | The WebAssemly spec removing the return value from store instructions, so remove the associated optimization from LLVM. This patch leaves the store instruction operands in place for now, so stores now always write to "$drop"; these will be removed in a seperate patch. llvm-svn: 279100
* Resubmit "Write the TPI stream from a PDB to Yaml."Zachary Turner2016-08-187-0/+1110
| | | | | | | | The original patch was breaking some buildbots due to an incorrect ordering of function definitions which caused some compilers to recognize a definition but others to not. llvm-svn: 279089
* llvm-objdump: add coff import library symbol listing supportSaleem Abdulrasool2016-08-182-0/+12
| | | | | | | | | | This adds behaviour similar to binutils' objdump which can show symbols in an import library. Differences from that stem around the fact that we do not create section symbols nor the all import import descriptor symbol reference. However, this does mean that the tool can serve as a possible replacement for the existing tool. llvm-svn: 279088
* CVP. Turn marking adds as no wrap (introduced by r278107) off by defaultArtur Pilipenko2016-08-181-1/+1
| | | | | | It causes a regression on our internal benchmark. Introduce cvp-dont-process flag and set it off by default while investigating the regression. llvm-svn: 279082
* [AArch64][GlobalISel] Select floating-point binary ops.Ahmed Bougacha2016-08-181-0/+245
| | | | | | There is no FREM instruction, but the others are straightforward. llvm-svn: 279081
* [GlobalISel] Add floating-point binary ops.Ahmed Bougacha2016-08-181-0/+55
| | | | llvm-svn: 279080
* [InstCombine] use m_APInt to allow icmp (mul X, Y), C folds for splat ↵Sanjay Patel2016-08-181-3/+1
| | | | | | | | | | | | constant vectors This is a sibling of: https://reviews.llvm.org/rL278859 https://reviews.llvm.org/rL278935 https://reviews.llvm.org/rL278945 https://reviews.llvm.org/rL279066 llvm-svn: 279077
* [WebAssembly] Refactor WebAssemblyLowerEmscriptenException pass for ↵Derek Schuff2016-08-182-9/+9
| | | | | | | | | | | | | | | | | | | | | | setjmp/longjmp This patch changes the code structure of WebAssemblyLowerEmscriptenException pass to support both exception handling and setjmp/longjmp. It also changes the name of the pass and the source file. 1. Change the file/pass name to WebAssemblyLowerEmscriptenExceptions -> WebAssemblyLowerEmscriptenEHSjLj to make it clear that it supports both EH and SjLj 2. List function / global variable names at the top so they can be changed easily 3. Some cosmetic changes Patch by Heejin Ahn Differential Revision: https://reviews.llvm.org/D23588 llvm-svn: 279075
* [AArch64][GlobalISel] Select G_SDIV/G_UDIV.Ahmed Bougacha2016-08-181-0/+126
| | | | | | | | There is no REM instruction; that will require an expansion. It's not obvious that should be done in select, rather than as a (custom?) legalization. llvm-svn: 279074
* [GlobalISel] Add support for DIV/REM.Ahmed Bougacha2016-08-181-0/+44
| | | | llvm-svn: 279073
* llvm-readobj: handle import libraries with -coff-exportsSaleem Abdulrasool2016-08-182-0/+22
| | | | | | | | `link -dump -exports` lists exported symbols from import libraries as well as normal dlls. Ensure that we can handle import libraries as well in llvm-readobj. llvm-svn: 279069
* [Hexagon] Create vcombine in HexagonCopyToCombineKrzysztof Parzyszek2016-08-181-0/+56
| | | | llvm-svn: 279067
* [InstCombine] use m_APInt to allow icmp (xor X, Y), C folds for splat ↵Sanjay Patel2016-08-184-16/+6
| | | | | | | | | | | constant vectors This is a sibling of: https://reviews.llvm.org/rL278859 https://reviews.llvm.org/rL278935 https://reviews.llvm.org/rL278945 llvm-svn: 279066
* [X86][SSE] Add SSE1 tests to make sure we don't merge loads on illegal typesSimon Pilgrim2016-08-181-123/+499
| | | | llvm-svn: 279065
* [mips] Correct tail call encoding for MIPSR6Simon Dardis2016-08-182-0/+43
| | | | | | | | | | | | | r277708 enabled tails calls for MIPS but used the 'jr' instruction when the jump target was held in a register. For MIPSR6, 'jalr $zero, $reg' should have been used. Additionally, add missing patterns for external and global symbols for tail calls. Reviewers: dsanders, vkalintiris Differential Review: https://reviews.llvm.org/D23301 llvm-svn: 279064
* [Reassociate] Add test for PR28367.Chad Rosier2016-08-181-0/+28
| | | | llvm-svn: 279063
* Testcase for r279022Matthias Braun2016-08-181-0/+24
| | | | llvm-svn: 279031
* [sanitizer-coverage/libFuzzer] instrument comparisons with ↵Kostya Serebryany2016-08-181-1/+1
| | | | | | __sanitizer_cov_trace_cmp[1248] instead of __sanitizer_cov_trace_cmp, don't pass the comparison type to save a bit performance. Use these new callbacks in libFuzzer llvm-svn: 279027
* Fix bot failure due to new testTeresa Johnson2016-08-181-1/+1
| | | | | | | I had updated the output file name but not the corresponding nm based check before submitting as r279023. This should fix the bot failures llvm-svn: 279025
* [ThinLTO] Keep common symbols in ThinLTO modulesTeresa Johnson2016-08-182-0/+51
| | | | | | | | | | | | | | | | | | | | Summary: Skip the merging of common symbols for ThinLTO modules, they will be merged by the final native object link. Trying to merge the symbols and add to a combined module will incorrectly enable the common symbol to be internalized in the ThinLTO module. Additionally, we will not want to create a combined module for ThinLTO distributed builds. This fixes failures in 7 cpu2006 benchmarks from the new LTO API in ThinLTO mode. Reviewers: mehdi_amini Subscribers: pcc, llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D23637 llvm-svn: 279023
* [LTO] Promote before performing weak resolutionMehdi Amini2016-08-181-0/+13
| | | | | | | | | | | | | | | | Summary: This was reversed compared to ThinLTOCodeGenerator for some reason, and lead to an increased code-size on my tests. I figured that the weak resolution may internalize a linkonce function, which will be promoted immediately (and renamed), before being internalized again. Reviewers: tejohnson Subscribers: pcc, llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D23632 llvm-svn: 279021
* [LTO] Change addSaveTemps API: do not add dot to the supplied prefix pathMehdi Amini2016-08-183-5/+5
| | | | | | | | | | | | | | | | Summary: It does not play well with directories (end up with a bunch of hidden files). Also, do not strip the 0 suffix for the first task, especially since 0 can be used by ThinLTO as well now. Reviewers: tejohnson Subscribers: mehdi_amini, pcc, llvm-commits Differential Revision: https://reviews.llvm.org/D23612 llvm-svn: 279014
* [WebAssembly] Handle debug information and virtual registers without ↵Dominic Chen2016-08-172-0/+77
| | | | | | | | | | | | | | crashing (reland r278967) Summary: Currently, enabling debug information when compiling for WebAssembly crashes the backend. This commit fixes these by skipping debug values in backend passes. Reviewers: jfb, aprantl, dschuff, echristo Subscribers: llvm-commits, dschuff, jfb, MatzeB, dexonsmith, yurydelendik, mehdi_amini Differential Revision: https://reviews.llvm.org/D23635 llvm-svn: 279011
* SCEV: Don't assert about non-SCEV-able value in isSCEVExprNeverPoison() ↵Hans Wennborg2016-08-171-0/+49
| | | | | | | | (PR28932) Differential Revision: https://reviews.llvm.org/D23594 llvm-svn: 278999
* [InstCombine] add test for missing vector icmp foldSanjay Patel2016-08-171-12/+36
| | | | | | | | Also, add a scalar test to demonstrate one of the intermediate folds that is necessary to accomplish the existing, multi-step test. And simplify the vector tests to only check the final piece of that multi-step transform. llvm-svn: 278995
* [macho2yaml] Don't write empty linkedit dataChris Bieneman2016-08-171-0/+1
| | | | | | | | Since I stopped writing empty export tries it causes LinkEdit to potentially be completely empty which results in invalid yaml being generated. To prevent this we skip linkedit data if it is empty. llvm-svn: 278985
* Revert "[WebAssembly] Handle debug information and virtual registers without ↵Duncan P. N. Exon Smith2016-08-171-75/+0
| | | | | | | | | | crashing" This reverts commit r278967, since the new test is failing when you don't build the WebAssembly target (most people, since it's off-by-default). llvm-svn: 278973
* GlobalISel: support irtranslation of icmp instructions.Tim Northover2016-08-171-0/+12
| | | | llvm-svn: 278969
* [WebAssembly] Handle debug information and virtual registers without crashingDominic Chen2016-08-171-0/+75
| | | | | | | | | | | | Summary: Currently, enabling debug information when compiling for WebAssembly crashes the backend. This commit fixes these by skipping debug values in backend passes. Reviewers: jfb, aprantl, dschuff, echristo Subscribers: mehdi_amini, yurydelendik, dexonsmith, MatzeB, jfb, dschuff, llvm-commits Differential Revision: https://reviews.llvm.org/D21808 llvm-svn: 278967
* [InstCombine] minimize tests and autogenerate checksSanjay Patel2016-08-171-32/+34
| | | | llvm-svn: 278960
* Fix for PR29010Marina Yatsina2016-08-171-0/+12
| | | | | | | | | | | This is a fix for https://llvm.org/bugs/show_bug.cgi?id=29010 Root cause of the bug is that the register class of the machine instruction operand does not fully reflect if this registers that can be allocated. Both for i386 and x86_64 the operand's register class is VR128RegClass and thus contains xmm0-xmm15, though in i386 we can only use xmm0-xmm8. In order to get the actual allocable registers of the class we need to use RegisterClassInfo. Differential Revision: https://reviews.llvm.org/D23613 llvm-svn: 278954
* Move tests to the appropriate subdirectory.Adrian Prantl2016-08-173-0/+0
| | | | llvm-svn: 278948
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