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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-08-18 15:17:01 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-08-18 15:17:01 +0000 |
| commit | 13db94540ca2647e6ee9577910f1fc2c1aedf32b (patch) | |
| tree | 1dc62abac8cc380adfcef8512138fa54d380a885 /llvm/test | |
| parent | 5b112845daf87b34530d3a2c06463bca7c6768ae (diff) | |
| download | bcm5719-llvm-13db94540ca2647e6ee9577910f1fc2c1aedf32b.tar.gz bcm5719-llvm-13db94540ca2647e6ee9577910f1fc2c1aedf32b.zip | |
[GlobalISel] Add support for DIV/REM.
llvm-svn: 279073
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll index 18c38fb6816..d2ecf3a104e 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll @@ -459,6 +459,50 @@ define i32 @test_ashr(i32 %arg1, i32 %arg2) { ret i32 %res } +; CHECK-LABEL: name: test_sdiv +; CHECK: [[ARG1:%[0-9]+]](32) = COPY %w0 +; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %w1 +; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_SDIV s32 [[ARG1]], [[ARG2]] +; CHECK-NEXT: %w0 = COPY [[RES]] +; CHECK-NEXT: RET_ReallyLR implicit %w0 +define i32 @test_sdiv(i32 %arg1, i32 %arg2) { + %res = sdiv i32 %arg1, %arg2 + ret i32 %res +} + +; CHECK-LABEL: name: test_udiv +; CHECK: [[ARG1:%[0-9]+]](32) = COPY %w0 +; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %w1 +; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_UDIV s32 [[ARG1]], [[ARG2]] +; CHECK-NEXT: %w0 = COPY [[RES]] +; CHECK-NEXT: RET_ReallyLR implicit %w0 +define i32 @test_udiv(i32 %arg1, i32 %arg2) { + %res = udiv i32 %arg1, %arg2 + ret i32 %res +} + +; CHECK-LABEL: name: test_srem +; CHECK: [[ARG1:%[0-9]+]](32) = COPY %w0 +; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %w1 +; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_SREM s32 [[ARG1]], [[ARG2]] +; CHECK-NEXT: %w0 = COPY [[RES]] +; CHECK-NEXT: RET_ReallyLR implicit %w0 +define i32 @test_srem(i32 %arg1, i32 %arg2) { + %res = srem i32 %arg1, %arg2 + ret i32 %res +} + +; CHECK-LABEL: name: test_urem +; CHECK: [[ARG1:%[0-9]+]](32) = COPY %w0 +; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %w1 +; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_UREM s32 [[ARG1]], [[ARG2]] +; CHECK-NEXT: %w0 = COPY [[RES]] +; CHECK-NEXT: RET_ReallyLR implicit %w0 +define i32 @test_urem(i32 %arg1, i32 %arg2) { + %res = urem i32 %arg1, %arg2 + ret i32 %res +} + ; CHECK-LABEL: name: test_constant_null ; CHECK: [[NULL:%[0-9]+]](64) = G_CONSTANT p0 0 ; CHECK: %x0 = COPY [[NULL]] |
