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* [mips][micromips] Implement DSBH, DSHD, DSLL, DSLL32, DSLLV, DSRA, DSRA32 ↵Hrvoje Varga2016-05-113-0/+23
| | | | | | | | and DSRAV instructions Differential Revision: http://reviews.llvm.org/D16800 llvm-svn: 269169
* [AArch64] Fix DAG selection for cmps for fp16 typeWeiming Zhao2016-05-111-0/+12
| | | | | | | | | | | | Summary: When emitting comparison for fp16, in addition to promote the LHS and RHS to fp32, we need to change the VT as well. Reviewers: t.p.northover Subscribers: t.p.northover, aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D19922 llvm-svn: 269151
* AMDGPU: Change private_element_size to 4Matt Arsenault2016-05-117-41/+81
| | | | llvm-svn: 269145
* Add missing tests for new PMXinliang David Li2016-05-102-0/+6
| | | | llvm-svn: 269139
* Revert r269131Easwaran Raman2016-05-102-38/+16
| | | | llvm-svn: 269138
* Propagate branch metadata when some branch probability is missing.Dehao Chen2016-05-101-1/+25
| | | | | | | | | | | | Summary: In sample profile, some branches may have profile missing due to profile inaccuracy. We want existing branch probability still valid after propagation. Reviewers: hfinkel, davidxl, spatel Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19948 llvm-svn: 269137
* auto-generate checksSanjay Patel2016-05-101-21/+68
| | | | llvm-svn: 269134
* AArch64: allow vN to represent 64-bit registers in inline asm.Tim Northover2016-05-101-0/+14
| | | | | | | | Unlike xN/wN, the size of vN is genuinely ambiguous in the assembly, so we should try to infer what was intended from the type. But only down to 64-bits (vN can never represent sN, hN or bN). llvm-svn: 269132
* Reapply r266477 and r266488Easwaran Raman2016-05-102-16/+38
| | | | llvm-svn: 269131
* [PM]: port IR based profUse pass to new pass managerXinliang David Li2016-05-1012-0/+16
| | | | llvm-svn: 269129
* remove some comments and other cruft from checksSanjay Patel2016-05-101-19/+15
| | | | llvm-svn: 269128
* Revert "MemCpyOpt: combine local load/store sequences into memcpy."Tim Northover2016-05-101-353/+0
| | | | | | | This reverts commit r269125. It was in my tree when I ran "git svn dcommit". It's really still under review. llvm-svn: 269127
* ARM: report an error when attempting to target a misalgined BLXTim Northover2016-05-102-0/+74
| | | | | | | The CodeGen problem was fixed in r269101, but we still miscompiled assembly that tried the same thing. llvm-svn: 269126
* MemCpyOpt: combine local load/store sequences into memcpy.Tim Northover2016-05-101-0/+353
| | | | | | | | Sort of the BB-local equivalent to idiom-recognizer: if we have a basic-block that really implements a memcpy operation, backends can benefit from seeing this. llvm-svn: 269125
* Loop unroller: set thresholds for optsize and minsize functions to zeroHans Wennborg2016-05-105-170/+36
| | | | | | | | | | | | | | | Before r268509, Clang would disable the loop unroll pass when optimizing for size. That commit enabled it to be able to support unroll pragmas in -Os builds. However, this regressed binary size in one of Chromium's DLLs with ~100 KB. This restores the original behaviour of no unrolling at -Os, but doing it in LLVM instead of Clang makes more sense, and also allows the pragmas to keep working. Differential revision: http://reviews.llvm.org/D20115 llvm-svn: 269124
* update test to use FileCheck for tighter checkingSanjay Patel2016-05-101-8/+114
| | | | llvm-svn: 269123
* update test to use FileCheck for tighter checkingSanjay Patel2016-05-101-3/+17
| | | | llvm-svn: 269122
* Enable loopreroll for sext of loop control only IVLawrence Hu2016-05-101-0/+186
| | | | | | | | | This patch extend loopreroll to allow the instruction chain of loop control only IV has sext. Differential Revision: http://reviews.llvm.org/D19820 llvm-svn: 269121
* Revert r26084: Enable loopreroll for sext of loop control only IVLawrence Hu2016-05-101-186/+0
| | | | llvm-svn: 269119
* Revert r269093: Enable loopreroll for sext of loop control only IVLawrence Hu2016-05-101-0/+186
| | | | llvm-svn: 269117
* [X86] Properly check that EAX is dead when copying EFLAGS.Quentin Colombet2016-05-101-0/+67
| | | | | | | | | | | | This fixes a bug introduced in r267623, where we got smarter and avoided to save EAX before using it. However, we failed to check if any of the subregister of EAX were alive and thus, missed cases where we have to save EAX before using it. The problem may happen on every X86/i386/... platform. This fixes llvm.org/PR27624 llvm-svn: 269115
* [InstSimplify] use computeKnownBits on shift amount operandsSanjay Patel2016-05-101-0/+147
| | | | | | | | | | | | | | Do simplifications common to all shift instructions based on the amount shifted: 1. If the shift amount is known larger than the bitwidth, the result is undefined. 2. If the valid bits of the shift amount are all known to be 0, it's a shift by zero, so the shift operand is the result. Note that we could generalize the shift-by-zero transform into a shift-by-constant if all of the valid bits in the shift amount are known, but that would have to be done in InstCombine rather than here because it would mean we need to create a new shift instruction. Differential Revision: http://reviews.llvm.org/D19874 llvm-svn: 269114
* [InstCombine] Fold icmp ugt/ult (udiv i32 C2, X), C1.Chad Rosier2016-05-101-0/+91
| | | | | | | | | | This patch adds support for two optimizations: icmp ugt (udiv C2, X), C1 -> icmp ule X, C2/(C1+1) icmp ult (udiv C2, X), C1 -> icmp ugt X, C2/C1 Differential Revision: http://reviews.llvm.org/D20123 llvm-svn: 269109
* [SystemZ] Add support for additional branch extended mnemonicsKit Barton2016-05-102-0/+108
| | | | | | | | | | | | | Added support for extended mnemonics for the following branch instructions and load/store-on-condition opcodes: BR, LOCR, LOCGR, LOC, LOCG, STOC, STOCG Phabricator: http://reviews.llvm.org/D19729 Committing on behalf of Zhan Liau llvm-svn: 269106
* [SCCP] Partially propagate informations when the input is not fully defined.Davide Italiano2016-05-101-0/+1
| | | | | | | | | | With this patch: %r1 = lshr i64 -1, 4294967296 -> undef Before this patch: %r1 = lshr i64 -1, 4294967296 -> 0 llvm-svn: 269105
* Debug Info: Prevent DW_AT_abstract_origin from being emitted twiceAdrian Prantl2016-05-101-0/+57
| | | | | | | | | | | | for the same subprogram. This fixes a bug where DW_AT_abstract_origin is being emitted twice for the same subprogram if a function is both inlined and emitted in the same translation unit, by restoring the pre-r266446 behavior. http://reviews.llvm.org/D20072 llvm-svn: 269103
* ARM: stop emitting blx instructions for most calls on MachO.Tim Northover2016-05-1026-166/+124
| | | | | | | | | | | I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
* LPM: Drop require<loops> from these tests, it's redundant. NFCJustin Bogner2016-05-102-2/+2
| | | | | | | | The LoopPassManager needs to calculate the loops analysis in order to iterate over the loops at all. Requiring it is redundant and just adds noise to the RUN lines here. llvm-svn: 269097
* Make "@name =" mandatory for globals in .ll files.Rafael Espindola2016-05-1029-98/+98
| | | | | | | | | | | | | | | | | | | | | | | An oddity of the .ll syntax is that the "@var = " in @var = global i32 42 is optional. Writing just global i32 42 is equivalent to @0 = global i32 42 This means that there is a pretty big First set at the top level. The current implementation maintains it manually. I was trying to refactor it, but then started wondering why keep it a all. I personally find the above syntax confusing. It looks like something is missing. This patch removes the feature and simplifies the parser. llvm-svn: 269096
* Enable loopreroll for sext of loop control only IVLawrence Hu2016-05-101-186/+0
| | | | | | | | | This patch extend loopreroll to allow the instruction chain of loop control only IV has sext. Differential Revision: http://reviews.llvm.org/D19820 llvm-svn: 269093
* Fix PR26655: Bail out if all regs of an inst BUNDLE have the correct kill flagMandeep Singh Grang2016-05-101-0/+41
| | | | | | | | | | | | | | | | | | | | Summary: While setting kill flags on instructions inside a BUNDLE, we bail out as soon as we set kill flag on a register. But we are missing a check when all the registers already have the correct kill flag set. We need to bail out in that case as well. This patch refactors the old code and simply makes use of the addRegisterKilled function in MachineInstr.cpp in order to determine whether to set/remove kill on an instruction. Reviewers: apazos, t.p.northover, pete, MatzeB Subscribers: MatzeB, davide, llvm-commits Differential Revision: http://reviews.llvm.org/D17356 llvm-svn: 269092
* [PGO] resubmit r268969Rong Xu2016-05-102-0/+13
| | | | | | Put the test into a target specific directory. llvm-svn: 269090
* Enable loopreroll for sext of loop control only IVLawrence Hu2016-05-101-0/+186
| | | | | | | This patch extend loopreroll to allow the instruction chain of loop control only IV has sext. llvm-svn: 269084
* [WebAssembly] Preliminary fast-isel support.Dan Gohman2016-05-108-5/+38
| | | | llvm-svn: 269083
* [X86][AVX512] Added another masked shuffle combine from load testSimon Pilgrim2016-05-101-0/+13
| | | | llvm-svn: 269077
* [ScheduleDAG] Make sure to process all def operands before any use operandsKrzysztof Parzyszek2016-05-101-0/+20
| | | | | | | | | | | | | | | | | An example from Hexagon where things went wrong: %R0<def> = L2_loadrigp <ga:@fp04> ; load function address J2_callr %R0<kill>, ..., %R0<imp-def> ; call *R0, return value in R0 ScheduleDAGInstrs::buildSchedGraph would visit all instructions going backwards, and in each instruction it would visit all operands in their order on the operand list. In the case of this call, it visited the use of R0 first, then removed it from the set Uses after it visited the def. This caused the DAG to be missing the data dependence edge on R0 between the load and the call. Differential Revision: http://reviews.llvm.org/D20102 llvm-svn: 269076
* [PR27599] [SystemZ] [SelectionDAG] Fix extension of atomic cmpxchg result.Marcin Koscielnicki2016-05-101-0/+81
| | | | | | | | | | | | Currently, SelectionDAG assumes 8/16-bit cmpxchg returns either a sign extended result, or a zero extended result. SystemZ takes a third option by returning junk in the high bits (rotated contents of the other bytes in the memory word). In that case, don't use Assert*ext, and zero-extend the result ourselves if a comparison is needed. Differential Revision: http://reviews.llvm.org/D19800 llvm-svn: 269075
* [X86][AVX] Added some shuffle combine from load testsSimon Pilgrim2016-05-102-0/+80
| | | | | | As discussed on D19198 - we need to check what happens when we shuffle with different value type to the load llvm-svn: 269068
* [ThinLTO] Add option to emit imports files for distributed backendsTeresa Johnson2016-05-103-0/+52
| | | | | | | | | | | | | | | | | | | | | Summary: Add support for emission of plaintext lists of the imported files for each distributed backend compilation. Used for distributed build file staging. Invoked with new gold-plugin thinlto-emit-imports-files option, which is only valid with thinlto-index-only (i.e. for distributed builds), or from llvm-lto with new -thinlto-action=emitimports value. Depends on D19556. Reviewers: joker.eph Subscribers: llvm-commits, joker.eph Differential Revision: http://reviews.llvm.org/D19636 llvm-svn: 269067
* Restore "[ThinLTO] Emit individual index files for distributed backends"Teresa Johnson2016-05-103-1/+86
| | | | | | | | | | | | | | | | | | | This restores commit r268627: Summary: When launching ThinLTO backends in a distributed build (currently supported in gold via the thinlto-index-only plugin option), emit an individual index file for each backend process as described here: http://lists.llvm.org/pipermail/llvm-dev/2016-April/098272.html ... Differential Revision: http://reviews.llvm.org/D19556 Address msan failures by avoiding std::prev on map.end(), the theory is that this is causing issues due to some known UB problems in __tree. llvm-svn: 269059
* Revert "[VectorUtils] Query number of sign bits to allow more truncations"James Molloy2016-05-101-36/+0
| | | | | | | | This was a fairly simple patch but on closer inspection was seriously flawed and caused PR27690. This reverts commit r268921. llvm-svn: 269051
* [mips][ias] Make the default path unreachable in needsRelocateWithSymbol() ↵Daniel Sanders2016-05-101-6/+6
| | | | | | | | | | | | | | | (except for N64). Following post-commit comments on r268900 from Rafael Espindola: The missing relocations are now explicitly listed in the switch statement with appropriate FIXME comments and the default path is now unreachable. The temporary exception to this is that compound relocations for N64 still have a default path that returns true. This is because fixing that case ought to be a separate patch. Also make R_MIPS_NONE return false since it has no effect on the section data. llvm-svn: 269047
* [OCaml] Update core test and re-enable testingJeroen Ketema2016-05-102-32/+7
| | | | | | Differential Revision: http://reviews.llvm.org/D19828 llvm-svn: 269040
* [X86][AVX512] Added masked version of MOVDDUP test with 16f32Simon Pilgrim2016-05-101-0/+20
| | | | llvm-svn: 269038
* Update Debug Intrinsics in RewriteUsesOfClonedInstructions in LoopRotationChuang-Yu Cheng2016-05-101-0/+39
| | | | | | | | | | | | | | | | | | | | | | Loop rotation clones instruction from the old header into the preheader. If there were uses of values produced by these instructions that were outside the loop, we have to insert PHI nodes to merge the two values. If the values are used by DbgIntrinsics they will be used as a MetadataAsValue of a ValueAsMetadata of the original values, and iterating all of the uses of the original value will not update the DbgIntrinsics. The new code checks if the values are used by DbgIntrinsics and if so, updates them using essentially the same logic as the original code. The attached testcase demonstrates the issue. Without the fix, the DbgIntrinic outside the loop uses values computed inside the loop, even though these values do not dominate the DbgIntrinsic. Author: Thomas Jablin (tjablin) Reviewers: dblaikie aprantl kbarton hfinkel cycheng http://reviews.llvm.org/D19564 llvm-svn: 269034
* [InstCombine] Remove trivially empty va_start/va_end and va_copy/va_end ranges.Arnaud A. de Grandmaison2016-05-101-0/+30
| | | | | | | | | | | | When a va_start or va_copy is immediately followed by a va_end (ignoring debug information or other start/end in between), then it is safe to remove the pair. As this code shares some commonalities with the lifetime markers, this has been factored to helper functions. This InstCombine pattern kicks-in 3 times when running the LLVM test suite. llvm-svn: 269033
* [Sparc][LEON] Itineraries unit test.Chris Dewhurst2016-05-101-0/+50
| | | | | | | | Added test to check LeonItineraries are being applied by code checked-in two weeks ago in r267121. Phabricator Review: http://reviews.llvm.org/D19359 llvm-svn: 269032
* Revert "[PGO] Fix __llvm_profile_raw_version linkage in MACHO IR ↵Renato Golin2016-05-101-10/+0
| | | | | | | | | | | | | instrumentation generates a COMDAT symbol __llvm_profile_raw_version to overwrite the same symbol in profile run-time to distinguish IR profiles from Clang generated profiles. In MACHO, LinkOnceODR linkage is used due to the lack of COMDAT support." This reverts commits r268969, r268979 and r268984. They had target specific test in generic directories without the correct specifiers and made it hard for us to come up with a good solution by rapidly committing untested changes. This test needs to be in a target specific directory or have the correct REQUIRED identifier. llvm-svn: 269027
* [foldMemoryOperand()] Pass LiveIntervals to enable liveness check.Jonas Paulsson2016-05-101-1/+1
| | | | | | | | | | | | | | | SystemZ (and probably other targets as well) can fold a memory operand by changing the opcode into a new instruction that as a side-effect also clobbers the CC-reg. In order to do this, liveness of that reg must first be checked. When LIS is passed, getRegUnit() can be called on it and the right LiveRange is computed on demand. Reviewed by Matthias Braun. http://reviews.llvm.org/D19861 llvm-svn: 269026
* [LoopVectorize] Handling induction variable with non-constant step.Elena Demikhovsky2016-05-101-0/+124
| | | | | | | | | | | | | | | | | | | | | | | Allow vectorization when the step is a loop-invariant variable. This is the loop example that is getting vectorized after the patch: int int_inc; int bar(int init, int *restrict A, int N) { int x = init; for (int i=0;i<N;i++){ A[i] = x; x += int_inc; } return x; } "x" is an induction variable with *loop-invariant* step. But it is not a primary induction. Primary induction variable with non-constant step is not handled yet. Differential Revision: http://reviews.llvm.org/D19258 llvm-svn: 269023
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