diff options
| author | Hrvoje Varga <Hrvoje.Varga@imgtec.com> | 2016-05-11 11:17:04 +0000 |
|---|---|---|
| committer | Hrvoje Varga <Hrvoje.Varga@imgtec.com> | 2016-05-11 11:17:04 +0000 |
| commit | aeb1fe8f200029df9da2fcd7c5e2c12ab408dd8f (patch) | |
| tree | dfcd11df63187688b2d61160457e0cafff7dd628 /llvm/test | |
| parent | b2ba5a546741785a1d16bd4d8e756dae2f71f286 (diff) | |
| download | bcm5719-llvm-aeb1fe8f200029df9da2fcd7c5e2c12ab408dd8f.tar.gz bcm5719-llvm-aeb1fe8f200029df9da2fcd7c5e2c12ab408dd8f.zip | |
[mips][micromips] Implement DSBH, DSHD, DSLL, DSLL32, DSLLV, DSRA, DSRA32 and DSRAV instructions
Differential Revision: http://reviews.llvm.org/D16800
llvm-svn: 269169
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt | 7 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/micromips64r6/invalid.s | 8 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/micromips64r6/valid.s | 8 |
3 files changed, 23 insertions, 0 deletions
diff --git a/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt index 58e27a490e1..66db06a5c79 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt @@ -258,3 +258,10 @@ 0x58 0xa4 0x18 0xd8 # CHECK: dmuhu $3, $4, $5 0x22 0x04 0x10 0x08 # CHECK: lwp $16, 8($4) 0x22 0x04 0x90 0x08 # CHECK: swp $16, 8($4) +0x58 0x64 0x7b 0x3c # CHECK: dsbh $3, $4 +0x58 0x64 0xfb 0x3c # CHECK: dshd $3, $4 +0x58 0x64 0x28 0x00 # CHECK: dsll $3, $4, 5 +0x58 0x64 0x28 0x08 # CHECK: dsll32 $3, $4, 5 +0x58 0xa6 0x20 0x10 # CHECK: dsllv $4, $5, $6 +0x58 0x85 0x28 0x80 # CHECK: dsra $4, $5, 5 +0x58 0xa6 0x20 0x90 # CHECK: dsrav $4, $5, $6 diff --git a/llvm/test/MC/Mips/micromips64r6/invalid.s b/llvm/test/MC/Mips/micromips64r6/invalid.s index c1c00dc5edf..2ddb9a31867 100644 --- a/llvm/test/MC/Mips/micromips64r6/invalid.s +++ b/llvm/test/MC/Mips/micromips64r6/invalid.s @@ -228,3 +228,11 @@ swp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset swp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset + dsll $3, $4, 64 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate + dsll $3, $4, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate + dsll32 $3, $4, 32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate + dsll32 $3, $4, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate + dsra $4, $5, 64 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate + dsra $4, $5, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate + dsra32 $4, $5, 32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate + dsra32 $4, $5, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate diff --git a/llvm/test/MC/Mips/micromips64r6/valid.s b/llvm/test/MC/Mips/micromips64r6/valid.s index b08bb7b5f62..cad295b1cb3 100644 --- a/llvm/test/MC/Mips/micromips64r6/valid.s +++ b/llvm/test/MC/Mips/micromips64r6/valid.s @@ -261,5 +261,13 @@ a: dmuhu $3, $4, $5 # CHECK dmuhu $3, $4, $5 # encoding: [0x58,0xa4,0x18,0xd8] lwp $16, 8($4) # CHECK: lwp $16, 8($4) # encoding: [0x22,0x04,0x10,0x08] swp $16, 8($4) # CHECK: swp $16, 8($4) # encoding: [0x22,0x04,0x90,0x08] + dsbh $3, $4 # CHECK: dsbh $3, $4 # encoding: [0x58,0x64,0x7b,0x3c] + dshd $3, $4 # CHECK: dshd $3, $4 # encoding: [0x58,0x64,0xfb,0x3c] + dsll $3, $4, 5 # CHECK: dsll $3, $4, 5 # encoding: [0x58,0x64,0x28,0x00] + dsll32 $3, $4, 5 # CHECK: dsll32 $3, $4, 5 # encoding: [0x58,0x64,0x28,0x08] + dsllv $4, $5, $6 # CHECK: dsllv $4, $5, $6 # encoding: [0x58,0xa6,0x20,0x10] + dsra $4, $5, 5 # CHECK: dsra $4, $5, 5 # encoding: [0x58,0x85,0x28,0x80] + dsra32 $4, $5, 5 # CHECK: dsra32 $4, $5, 5 # encoding: [0x58,0x85,0x28,0x84] + dsrav $4, $5, $6 # CHECK: dsrav $4, $5, $6 # encoding: [0x58,0xa6,0x20,0x90] 1: |
